60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
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/*
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* Copyright 2020-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SCFG_H
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#define SCFG_H
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#ifdef CONFIG_CHASSIS_2
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/* SCFG register offsets */
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#define SCFG_CORE0_SFT_RST_OFFSET 0x0130
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#define SCFG_SNPCNFGCR_OFFSET 0x01A4
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#define SCFG_CORESRENCR_OFFSET 0x0204
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#define SCFG_RVBAR0_0_OFFSET 0x0220
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#define SCFG_RVBAR0_1_OFFSET 0x0224
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#define SCFG_COREBCR_OFFSET 0x0680
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#define SCFG_RETREQCR_OFFSET 0x0424
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#define SCFG_COREPMCR_OFFSET 0x042C
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#define COREPMCR_WFIL2 0x1
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#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188
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#define SCFG_BOOTLOCPTRH_OFFSET 0x0600
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#define SCFG_BOOTLOCPTRL_OFFSET 0x0604
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#define SCFG_SCRATCHRW2_OFFSET 0x0608
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#define SCFG_SCRATCHRW3_OFFSET 0x060C
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/* SCFG bit fields */
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#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
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#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
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#endif /* CONFIG_CHASSIS_2 */
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#ifndef __ASSEMBLER__
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#include <endian.h>
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#include <lib/mmio.h>
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#ifdef NXP_SCFG_BE
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#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
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#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
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#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
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#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
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#define scfg_clrsetbits32(a, clear, set) \
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mmio_clrsetbits_32((uintptr_t)(a), clear, set)
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#elif defined(NXP_GUR_LE)
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#define scfg_in32(a) mmio_read_32((uintptr_t)(a))
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#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v)
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#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
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#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
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#define scfg_clrsetbits32(a, clear, set) \
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mmio_clrsetbits_32((uintptr_t)(a), clear, set)
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#else
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#error Please define CCSR SCFG register endianness
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#endif
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#endif /* __ASSEMBLER__ */
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#endif /* SCFG_H */
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