338 lines
9.9 KiB
C
338 lines
9.9 KiB
C
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/*
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* Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SD_MMC_H
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#define SD_MMC_H
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#include <lib/mmio.h>
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/* operating freq */
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#define CARD_IDENTIFICATION_FREQ 400000
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#define SD_SS_25MHZ 20000000
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#define SD_HS_50MHZ 40000000
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#define MMC_SS_20MHZ 15000000
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#define MMC_HS_26MHZ 20000000
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#define MMC_HS_52MHZ 40000000
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/* Need to check this value ? */
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#define MAX_PLATFORM_CLOCK 800000000
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/* eSDHC system control register defines */
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#define ESDHC_SYSCTL_DTOCV(t) (((t) & 0xF) << 16)
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#define ESDHC_SYSCTL_SDCLKFS(f) (((f) & 0xFF) << 8)
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#define ESDHC_SYSCTL_DVS(d) (((d) & 0xF) << 4)
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#define ESDHC_SYSCTL_SDCLKEN (0x00000008)
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#define ESDHC_SYSCTL_RSTA (0x01000000)
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/* Data timeout counter value. SDHC_CLK x 227 */
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#define TIMEOUT_COUNTER_SDCLK_2_27 0xE
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#define ESDHC_SYSCTL_INITA 0x08000000
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/* eSDHC interrupt status enable register defines */
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#define ESDHC_IRQSTATEN_CINS 0x00000040
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#define ESDHC_IRQSTATEN_BWR 0x00000010
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/* eSDHC interrupt status register defines */
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#define ESDHC_IRQSTAT_DMAE (0x10000000)
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#define ESDHC_IRQSTAT_AC12E (0x01000000)
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#define ESDHC_IRQSTAT_DEBE (0x00400000)
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#define ESDHC_IRQSTAT_DCE (0x00200000)
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#define ESDHC_IRQSTAT_DTOE (0x00100000)
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#define ESDHC_IRQSTAT_CIE (0x00080000)
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#define ESDHC_IRQSTAT_CEBE (0x00040000)
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#define ESDHC_IRQSTAT_CCE (0x00020000)
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#define ESDHC_IRQSTAT_CTOE (0x00010000)
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#define ESDHC_IRQSTAT_CINT (0x00000100)
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#define ESDHC_IRQSTAT_CRM (0x00000080)
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#define ESDHC_IRQSTAT_CINS (0x00000040)
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#define ESDHC_IRQSTAT_BRR (0x00000020)
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#define ESDHC_IRQSTAT_BWR (0x00000010)
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#define ESDHC_IRQSTAT_DINT (0x00000008)
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#define ESDHC_IRQSTAT_BGE (0x00000004)
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#define ESDHC_IRQSTAT_TC (0x00000002)
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#define ESDHC_IRQSTAT_CC (0x00000001)
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#define ESDHC_IRQSTAT_CMD_ERR (ESDHC_IRQSTAT_CIE |\
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ESDHC_IRQSTAT_CEBE |\
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ESDHC_IRQSTAT_CCE)
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#define ESDHC_IRQSTAT_DATA_ERR (ESDHC_IRQSTAT_DEBE |\
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ESDHC_IRQSTAT_DCE |\
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ESDHC_IRQSTAT_DTOE)
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#define ESDHC_IRQSTAT_CLEAR_ALL (0xFFFFFFFF)
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/* eSDHC present state register defines */
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#define ESDHC_PRSSTAT_CLSL 0x00800000
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#define ESDHC_PRSSTAT_WPSPL 0x00080000
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#define ESDHC_PRSSTAT_CDPL 0x00040000
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#define ESDHC_PRSSTAT_CINS 0x00010000
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#define ESDHC_PRSSTAT_BREN 0x00000800
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#define ESDHC_PRSSTAT_BWEN 0x00000400
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#define ESDHC_PRSSTAT_RTA 0x00000200
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#define ESDHC_PRSSTAT_WTA 0x00000100
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#define ESDHC_PRSSTAT_SDOFF 0x00000080
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#define ESDHC_PRSSTAT_PEROFF 0x00000040
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#define ESDHC_PRSSTAT_HCKOFF 0x00000020
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#define ESDHC_PRSSTAT_IPGOFF 0x00000010
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#define ESDHC_PRSSTAT_DLA 0x00000004
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#define ESDHC_PRSSTAT_CDIHB 0x00000002
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#define ESDHC_PRSSTAT_CIHB 0x00000001
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/* eSDHC protocol control register defines */
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#define ESDHC_PROCTL_EMODE_LE 0x00000020
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#define ESDHC_PROCTL_DTW_1BIT 0x00000000
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#define ESDHC_PROCTL_DTW_4BIT 0x00000002
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#define ESDHC_PROCTL_DTW_8BIT 0x00000004
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/* Watermark Level Register (WML) */
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#define ESDHC_WML_RD_WML(w) ((w) & 0x7F)
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#define ESDHC_WML_WR_WML(w) (((w) & 0x7F) << 16)
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#define ESDHC_WML_RD_BRST(w) (((w) & 0xF) << 8)
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#define ESDHC_WML_WR_BRST(w) (((w) & 0xF) << 24)
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#define ESDHC_WML_WR_BRST_MASK (0x0F000000)
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#define ESDHC_WML_RD_BRST_MASK (0x00000F00)
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#define ESDHC_WML_RD_WML_MASK (0x0000007F)
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#define ESDHC_WML_WR_WML_MASK (0x007F0000)
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#define WML_512_BYTES (0x0)
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#define BURST_128_BYTES (0x0)
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/* eSDHC control register define */
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#define ESDHC_DCR_SNOOP 0x00000040
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/* ESDHC Block attributes register */
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#define ESDHC_BLKATTR_BLKCNT(c) (((c) & 0xffff) << 16)
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#define ESDHC_BLKATTR_BLKSZE(s) ((s) & 0xfff)
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/* Transfer Type Register */
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#define ESDHC_XFERTYP_CMD(c) (((c) & 0x3F) << 24)
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#define ESDHC_XFERTYP_CMDTYP_NORMAL (0x0)
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#define ESDHC_XFERTYP_CMDTYP_SUSPEND (0x00400000)
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#define ESDHC_XFERTYP_CMDTYP_RESUME (0x00800000)
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#define ESDHC_XFERTYP_CMDTYP_ABORT (0x00C00000)
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#define ESDHC_XFERTYP_DPSEL (0x00200000)
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#define ESDHC_XFERTYP_CICEN (0x00100000)
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#define ESDHC_XFERTYP_CCCEN (0x00080000)
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#define ESDHC_XFERTYP_RSPTYP_NONE (0x0)
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#define ESDHC_XFERTYP_RSPTYP_136 (0x00010000)
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#define ESDHC_XFERTYP_RSPTYP_48 (0x00020000)
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#define ESDHC_XFERTYP_RSPTYP_48_BUSY (0x00030000)
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#define ESDHC_XFERTYP_MSBSEL (0x00000020)
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#define ESDHC_XFERTYP_DTDSEL (0x00000010)
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#define ESDHC_XFERTYP_AC12EN (0x00000004)
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#define ESDHC_XFERTYP_BCEN (0x00000002)
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#define ESDHC_XFERTYP_DMAEN (0x00000001)
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#define MMC_VDD_HIGH_VOLTAGE 0x00000100
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/* command index */
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#define CMD0 0
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#define CMD1 1
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#define CMD2 2
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#define CMD3 3
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#define CMD5 5
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#define CMD6 6
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#define CMD7 7
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#define CMD8 8
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#define CMD9 9
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#define CMD12 12
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#define CMD13 13
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#define CMD14 14
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#define CMD16 16
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#define CMD17 17
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#define CMD18 18
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#define CMD19 19
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#define CMD24 24
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#define CMD41 41
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#define CMD42 42
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#define CMD51 51
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#define CMD55 55
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#define CMD56 56
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#define ACMD6 CMD6
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#define ACMD13 CMD13
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#define ACMD41 CMD41
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#define ACMD42 CMD42
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#define ACMD51 CMD51
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/* commands abbreviations */
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#define CMD_GO_IDLE_STATE CMD0
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#define CMD_MMC_SEND_OP_COND CMD1
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#define CMD_ALL_SEND_CID CMD2
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#define CMD_SEND_RELATIVE_ADDR CMD3
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#define CMD_SET_DSR CMD4
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#define CMD_SWITCH_FUNC CMD6
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#define CMD_SELECT_CARD CMD7
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#define CMD_DESELECT_CARD CMD7
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#define CMD_SEND_IF_COND CMD8
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#define CMD_MMC_SEND_EXT_CSD CMD8
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#define CMD_SEND_CSD CMD9
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#define CMD_SEND_CID CMD10
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#define CMD_STOP_TRANSMISSION CMD12
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#define CMD_SEND_STATUS CMD13
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#define CMD_BUS_TEST_R CMD14
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#define CMD_GO_INACTIVE_STATE CMD15
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#define CMD_SET_BLOCKLEN CMD16
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#define CMD_READ_SINGLE_BLOCK CMD17
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#define CMD_READ_MULTIPLE_BLOCK CMD18
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#define CMD_WRITE_SINGLE_BLOCK CMD24
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#define CMD_BUS_TEST_W CMD19
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#define CMD_APP_CMD CMD55
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#define CMD_GEN_CMD CMD56
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#define CMD_SET_BUS_WIDTH ACMD6
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#define CMD_SD_STATUS ACMD13
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#define CMD_SD_SEND_OP_COND ACMD41
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#define CMD_SET_CLR_CARD_DETECT ACMD42
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#define CMD_SEND_SCR ACMD51
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/* MMC card spec version */
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#define MMC_CARD_VERSION_1_2 0
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#define MMC_CARD_VERSION_1_4 1
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#define MMC_CARD_VERSION_2_X 2
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#define MMC_CARD_VERSION_3_X 3
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#define MMC_CARD_VERSION_4_X 4
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/* SD Card Spec Version */
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/* May need to add version 3 here? */
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#define SD_CARD_VERSION_1_0 0
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#define SD_CARD_VERSION_1_10 1
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#define SD_CARD_VERSION_2_0 2
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/* card types */
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#define MMC_CARD 0
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#define SD_CARD 1
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#define NOT_SD_CARD MMC_CARD
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/* Card rca */
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#define SD_MMC_CARD_RCA 0x1
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#define BLOCK_LEN_512 512
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/* card state */
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#define STATE_IDLE 0
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#define STATE_READY 1
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#define STATE_IDENT 2
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#define STATE_STBY 3
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#define STATE_TRAN 4
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#define STATE_DATA 5
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#define STATE_RCV 6
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#define STATE_PRG 7
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#define STATE_DIS 8
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/* Card OCR register */
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/* VDD voltage window 1,65 to 1.95 */
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#define MMC_OCR_VDD_165_195 0x00000080
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/* VDD voltage window 2.7-2.8 */
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#define MMC_OCR_VDD_FF8 0x00FF8000
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#define MMC_OCR_CCS 0x40000000/* Card Capacity */
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#define MMC_OCR_BUSY 0x80000000/* busy bit */
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#define SD_OCR_HCS 0x40000000/* High capacity host */
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#define MMC_OCR_SECTOR_MODE 0x40000000/* Access Mode as Sector */
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/* mmc Switch function */
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#define SET_EXT_CSD_HS_TIMING 0x03B90100/* set High speed */
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/* check supports switching or not */
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#define SD_SWITCH_FUNC_CHECK_MODE 0x00FFFFF1
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#define SD_SWITCH_FUNC_SWITCH_MODE 0x80FFFFF1/* switch */
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#define SD_SWITCH_FUNC_HIGH_SPEED 0x02/* HIGH SPEED FUNC */
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#define SWITCH_ERROR 0x00000080
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/* errors in sending commands */
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#define RESP_TIMEOUT 0x1
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#define COMMAND_ERROR 0x2
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/* error in response */
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#define R1_ERROR (1 << 19)
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#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9)
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/* Host Controller Capabilities */
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#define ESDHC_HOSTCAPBLT_DMAS (0x00400000)
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/* SD/MMC memory map */
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struct esdhc_regs {
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uint32_t dsaddr; /* dma system address */
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uint32_t blkattr; /* Block attributes */
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uint32_t cmdarg; /* Command argument */
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uint32_t xfertyp; /* Command transfer type */
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uint32_t cmdrsp[4]; /* Command response0,1,2,3 */
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uint32_t datport; /* Data buffer access port */
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uint32_t prsstat; /* Present state */
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uint32_t proctl; /* Protocol control */
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uint32_t sysctl; /* System control */
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uint32_t irqstat; /* Interrupt status */
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uint32_t irqstaten; /* Interrupt status enable */
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uint32_t irqsigen; /* Interrupt signal enable */
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uint32_t autoc12err; /* Auto CMD12 status */
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uint32_t hostcapblt; /* Host controller capabilities */
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uint32_t wml; /* Watermark level */
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uint32_t res1[2];
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uint32_t fevt; /* Force event */
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uint32_t res2;
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uint32_t adsaddrl;
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uint32_t adsaddrh;
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uint32_t res3[39];
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uint32_t hostver; /* Host controller version */
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uint32_t res4;
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uint32_t dmaerr; /* DMA error address */
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uint32_t dmaerrh; /* DMA error address high */
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uint32_t dmaerrattr; /* DMA error atrribute */
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uint32_t res5;
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uint32_t hostcapblt2;/* Host controller capabilities2 */
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uint32_t res6[2];
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uint32_t tcr; /* Tuning control */
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uint32_t res7[7];
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uint32_t dirctrl; /* Direction control */
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uint32_t ccr; /* Clock control */
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uint32_t res8[177];
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uint32_t ctl; /* Control register */
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};
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/* SD/MMC card attributes */
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struct card_attributes {
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uint32_t type; /* sd or mmc card */
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uint32_t version; /* version */
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uint32_t block_len; /* block length */
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uint32_t bus_freq; /* sdhc bus frequency */
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uint16_t rca; /* relative card address */
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uint8_t is_high_capacity; /* high capacity */
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};
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struct mmc {
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struct esdhc_regs *esdhc_regs;
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struct card_attributes card;
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uint32_t block_len;
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uint32_t voltages_caps; /* supported voltaes */
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uint32_t dma_support; /* DMA support */
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};
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enum cntrl_num {
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SDHC1 = 0,
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SDHC2
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};
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int sd_emmc_init(uintptr_t *block_dev_spec,
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uintptr_t nxp_esdhc_addr,
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size_t nxp_sd_block_offset,
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size_t nxp_sd_block_size,
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bool card_detect);
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int esdhc_emmc_init(struct mmc *mmc, bool card_detect);
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int esdhc_read(struct mmc *mmc, uint32_t src_offset, uintptr_t dst,
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size_t size);
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int esdhc_write(struct mmc *mmc, uintptr_t src, uint32_t dst_offset,
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size_t size);
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#ifdef NXP_ESDHC_BE
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#define esdhc_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
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#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
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#elif defined(NXP_ESDHC_LE)
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#define esdhc_in32(a) mmio_read_32((uintptr_t)(a))
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#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
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#else
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#error Please define CCSR ESDHC register endianness
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#endif
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#endif /*SD_MMC_H*/
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