87 lines
2.5 KiB
C
87 lines
2.5 KiB
C
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SNVS_H
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#define SNVS_H
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#ifndef __ASSEMBLER__
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#include <endian.h>
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#include <stdbool.h>
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#include <lib/mmio.h>
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struct snvs_regs {
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uint32_t reserved1;
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uint32_t hp_com; /* 0x04 SNVS_HP Command Register */
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uint32_t reserved2[3];
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uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */
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};
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#ifdef NXP_SNVS_BE
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#define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
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#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v)))
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#elif defined(NXP_SNVS_LE)
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#define snvs_read32(a) mmio_read_32((uintptr_t)(a))
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#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
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#else
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#error Please define CCSR SNVS register endianness
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#endif
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void snvs_init(uintptr_t nxp_snvs_addr);
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uint32_t get_snvs_state(void);
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void transition_snvs_non_secure(void);
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void transition_snvs_soft_fail(void);
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uint32_t transition_snvs_trusted(void);
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uint32_t transition_snvs_secure(void);
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uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos);
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void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val);
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void snvs_disable_zeroize_lp_gpr(void);
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#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB)
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uint32_t snvs_read_app_data(void);
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uint32_t snvs_read_app_data_bit(uint32_t bit_pos);
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void snvs_clear_app_data(void);
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void snvs_write_app_data_bit(uint32_t bit_pos);
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#endif
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#endif /* __ASSEMBLER__ */
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/* SSM_ST field in SNVS status reg */
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#define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */
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#define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */
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#define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */
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#define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */
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#define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */
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#define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */
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/* SNVS register bits */
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#define HPCOM_SW_SV 0x100 /* Security Violation bit */
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#define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */
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#define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */
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#define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
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#define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
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#define NXP_LP_GPR0_OFFSET 0x90
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#define NXP_LPCR_OFFSET 0x38
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#define NXP_GPR_Z_DIS_BIT 24
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#ifdef NXP_COINED_BB
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#ifndef NXP_APP_DATA_LP_GPR_OFFSET
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#define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET
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#endif
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#define NXP_LPGPR_ZEROTH_BIT 0
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#endif /* NXP_COINED_BB */
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#endif /* SNVS_H */
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