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android13/kernel-5.10/arch/arm/boot/dts/rk3128x.dtsi

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2024-06-22 08:45:49 -04:00
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/power/rk3228-power.h>
#include <dt-bindings/suspend/rockchip-rk322x.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include "rk322x-dram-default-timing.dtsi"
#include "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
spi0 = &spi0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
enable-method = "psci";
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <122>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
enable-method = "psci";
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
enable-method = "psci";
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
enable-method = "psci";
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
rockchip,avs = <1>;
rockchip,leakage-scaling-sel = <
0 254 20
>;
clocks = <&cru PLL_APLL>;
rockchip,max-volt = <1350000>;
rockchip,leakage-voltage-sel = <
1 4 0
5 254 1
>;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "cpu_leakage";
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1200000>;
opp-microvolt-L0 = <950000 950000 1200000>;
opp-microvolt-L1 = <950000 950000 1200000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <975000 975000 1200000>;
opp-microvolt-L0 = <975000 975000 1200000>;
opp-microvolt-L1 = <975000 975000 1200000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000 1000000 1200000>;
opp-microvolt-L0 = <1000000 1000000 1200000>;
opp-microvolt-L1 = <1000000 1000000 1200000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1175000 1175000 1200000>;
opp-microvolt-L0 = <1175000 1175000 1200000>;
opp-microvolt-L1 = <1125000 1125000 1200000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1175000 1175000 1200000>;
opp-microvolt-L0 = <1175000 1175000 1200000>;
opp-microvolt-L1 = <1125000 1125000 1200000>;
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma: pdma@110f0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x110f0000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
arm,pl330-periph-burst;
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
dmc: dmc {
compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram";
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 330000
>;
dram_freq = <330000000>;
rockchip,dram_timing = <&dram_timing>;
#cooling-cells = <2>;
status = "disabled";
ddr_power_model: ddr_power_model {
compatible = "ddr_power_model";
dynamic-power-coefficient = <120>;
static-power-coefficient = <200>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
};
};
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
rockchip,leakage-voltage-sel = <
1 5 0
6 254 1
>;
nvmem-cells = <&logic_leakage>;
nvmem-cell-names = "ddr_leakage";
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
opp-330000000 {
opp-hz = /bits/ 64 <330000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
status = "disabled";
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000>;
opp-microvolt-L0 = <1100000>;
opp-microvolt-L1 = <1050000>;
status = "disabled";
};
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <1150000>;
opp-microvolt-L0 = <1150000>;
opp-microvolt-L1 = <1100000>;
status = "disabled";
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <1150000>;
opp-microvolt-L0 = <1150000>;
opp-microvolt-L1 = <1100000>;
status = "disabled";
};
opp-786000000 {
opp-hz = /bits/ 64 <786000000>;
opp-microvolt = <1150000>;
opp-microvolt-L0 = <1150000>;
opp-microvolt-L1 = <1100000>;
status = "disabled";
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1150000>;
opp-microvolt-L0 = <1150000>;
opp-microvolt-L1 = <1100000>;
status = "disabled";
};
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
i2s1: i2s1@100b0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
dmas = <&pdma 14>, <&pdma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
status = "disabled";
};
i2s0: i2s0@100c0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100c0000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
dmas = <&pdma 11>, <&pdma 12>;
dma-names = "tx", "rx";
status = "disabled";
};
spdif: spdif@100d0000 {
compatible = "rockchip,rk3228-spdif";
reg = <0x100d0000 0x1000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
clock-names = "mclk", "hclk";
dmas = <&pdma 10>;
#dma-cells = <1>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
status = "disabled";
};
i2s2: i2s2@100e0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100e0000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
dmas = <&pdma 0>, <&pdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
tsp: tsp@100f0000 {
compatible = "rockchip,rk3228-tsp";
reg = <0x100f0000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_tsp";
clocks = <&cru SCLK_TSP>, <&cru HCLK_TSP>, <&cru SCLK_HSADC>;
clock-names = "clk_tsp", "hclk_tsp", "aclk_tsp";
pinctrl-names = "default";
pinctrl-0 = <&tsp_d0
&tsp_d1
&tsp_d2
&tsp_d3
&tsp_d4
&tsp_d5
&tsp_d6
&tsp_d7
&tsp_sync
&tsp_clk
&tsp_fail
&tsp_valid>;
status = "disabled";
};
grf: syscon@11000000 {
compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
reg = <0x11000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
io_domains: io-domains {
compatible = "rockchip,rk322x-io-voltage-domain";
status = "disabled";
};
reboot_mode: reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x5c8>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-bootloader = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
mode-ums = <BOOT_UMS>;
};
u2phy0: usb2-phy@760 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0760 0x0c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy0";
status = "disabled";
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
u2phy0_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
};
u2phy1: usb2-phy@800 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0800 0x0c>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy1";
status = "disabled";
u2phy1_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
u2phy1_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
};
power: power-controller {
compatible = "rockchip,rk3228-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pd_vpu@RK3228_PD_VPU {
reg = <RK3228_PD_VPU>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
pm_qos = <&qos_vpu>;
};
pd_rkvdec@RK3228_PD_RKVDEC {
reg = <RK3228_PD_RKVDEC>;
clocks = <&cru ACLK_RKVDEC>,
<&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>,
<&cru SCLK_VDEC_CORE>;
pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>;
};
};
};
uart0: serial@11010000 {
compatible = "snps,dw-apb-uart";
reg = <0x11010000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@11020000 {
compatible = "snps,dw-apb-uart";
reg = <0x11020000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@11030000 {
compatible = "snps,dw-apb-uart";
reg = <0x11030000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart21_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
efuse: efuse@11040000 {
compatible = "rockchip,rk322x-efuse";
reg = <0x11040000 0x20>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE_256>;
clock-names = "pclk_efuse";
/* Data cells */
efuse_id: id@7 {
reg = <0x7 0x10>;
};
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
logic_leakage: logic-leakage@19 {
reg = <0x19 0x1>;
};
hdmi_phy_flag: hdmi_phy_flag@1d {
reg = <0x1d 0x1>;
bits = <1 1>;
};
tve_dac: tve_dac@1d {
reg = <0x1d 0x1>;
bits = <3 5>;
};
};
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
status = "disabled";
};
i2c1: i2c@11060000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11060000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
i2c2: i2c@11070000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11070000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
i2c3: i2c@11080000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11080000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
status = "disabled";
};
spi0: spi@11090000 {
compatible = "rockchip,rk3228-spi";
reg = <0x11090000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
status = "disabled";
};
wdt: watchdog@110a0000 {
compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";
reg = <0x110a0000 0x100>;
clocks = <&cru PCLK_CPU>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pwm0: pwm@110b0000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
};
pwm1: pwm@110b0010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
};
pwm2: pwm@110b0020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
};
pwm3: pwm@110b0030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0030 0x10>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};
timer: timer@110c0000 {
compatible = "rockchip,rk3288-timer";
reg = <0x110c0000 0x20>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
clock-names = "timer", "pclk";
};
cru: clock-controller@110e0000 {
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru PLL_GPLL>, <&cru ARMCLK>,
<&cru PLL_CPLL>, <&cru ACLK_PERI>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
<&cru ACLK_CPU>, <&cru HCLK_CPU>,
<&cru PCLK_CPU>, <&cru ACLK_VOP>;
assigned-clock-rates =
<1200000000>, <816000000>,
<500000000>, <150000000>,
<150000000>, <75000000>,
<150000000>, <150000000>,
<75000000>, <400000000>;
};
thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
sustainable-power = <1200>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
trips {
threshold: trip-point@0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
target: trip-point@1 {
temperature = <85000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
soc_crit: soc-crit {
temperature = <115000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map1 {
trip = <&target>;
cooling-device =
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map2 {
trip = <&target>;
cooling-device =
<&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map3 {
trip = <&target>;
cooling-device =
<&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
};
tsadc: tsadc@11150000 {
compatible = "rockchip,rk3228-tsadc";
reg = <0x11150000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <32768>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "gpio", "otpout";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <0>;
rockchip,hw-tshut-temp = <120000>;
status = "disabled";
};
codec: codec@12010000 {
compatible = "rockchip,rk3228-codec";
reg = <0x12010000 0x1000>;
clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
clock-names = "mclk", "pclk", "sclk";
spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
hdmi_phy: hdmi-phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";
reg = <0x12030000 0x10000>;
#phy-cells = <0>;
clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>;
clock-names = "sysclk", "refclk";
#clock-cells = <0>;
clock-output-names = "hdmiphy_phy";
nvmem-cells = <&hdmi_phy_flag>;
nvmem-cell-names = "hdmi_phy_flag";
rockchip,phy-table =
<190000000 0xaa 0x00 0x44 0x44 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00>;
status = "disabled";
};
gpu: gpu@0x20001000 {
compatible = "arm,mali400";
reg = <0x20001000 0x200>,
<0x20000000 0x100>,
<0x20003000 0x100>,
<0x20008000 0x1100>,
<0x20004000 0x100>,
<0x2000A000 0x1100>,
<0x20005000 0x100>;
reg-names = "Mali_L2",
"Mali_GP",
"Mali_GP_MMU",
"Mali_PP0",
"Mali_PP0_MMU",
"Mali_PP1",
"Mali_PP1_MMU";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "Mali_GP_IRQ",
"Mali_GP_MMU_IRQ",
"Mali_PP0_IRQ",
"Mali_PP0_MMU_IRQ",
"Mali_PP1_IRQ",
"Mali_PP1_MMU_IRQ";
clocks = <&cru ACLK_GPU>;
#cooling-cells = <2>; /* min followed by max */
clock-names = "clk_mali";
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
gpu_power_model: power_model {
compatible = "arm,mali-simple-power-model";
voltage = <900>;
frequency = <500>;
static-power = <300>;
dynamic-power = <396>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
};
};
gpu_opp_table: opp-table2 {
compatible = "operating-points-v2";
rockchip,leakage-voltage-sel = <
1 5 0
6 254 1
>;
nvmem-cells = <&logic_leakage>;
nvmem-cell-names = "gpu_leakage";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
opp-microvolt-L0 = <1125000>;
opp-microvolt-L1 = <1100000>;
};
};
vpu_service: vpu-service@20020000 {
compatible = "rockchip,vpu_service";
reg = <0x20020000 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec", "irq_enc";
resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>;
reset-names = "video_a", "video_h";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
power-domains = <&power RK3228_PD_VPU>;
rockchip,grf = <&grf>;
iommus = <&vpu_mmu>;
allocator = <1>;
status = "disabled";
};
vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";
reg = <0x20020800 0x40>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
power-domains = <&power RK3228_PD_VPU>;
#iommu-cells = <0>;
status = "disabled";
};
rkvdec: rkvdec@20030000 {
compatible = "rockchip,rkvdec";
reg = <0x20030000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac",
"clk_core";
resets = <&cru SRST_RKVDEC_A>, <&cru SRST_RKVDEC_H>,
<&cru SRST_RKVDEC_NOC_A>, <&cru SRST_RKVDEC_NOC_H>,
<&cru SRST_RKVDEC_CABAC>, <&cru SRST_RKVDEC_CORE>;
reset-names = "video_a", "video_h", "niu_a", "niu_h",
"video_cabac", "video_core";
power-domains = <&power RK3228_PD_RKVDEC>;
operating-points-v2 = <&rkvdec_opp_table>;
#cooling-cells = <2>;
rockchip,grf = <&grf>;
iommus = <&rkvdec_mmu>;
allocator = <1>;
status = "disabled";
vcodec_power_model: vcodec_power_model {
compatible = "vcodec_power_model";
dynamic-power-coefficient = <120>;
static-power-coefficient = <200>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
};
};
rkvdec_opp_table: rkvdec-opp-table {
compatible = "operating-points-v2";
rockchip,leakage-voltage-sel = <
1 5 0
6 254 1
>;
nvmem-cells = <&logic_leakage>;
nvmem-cell-names = "rkvdec_leakage";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1050000>;
opp-microvolt-L0 = <1050000>;
opp-microvolt-L1 = <1000000>;
};
};
rkvdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3228_PD_RKVDEC>;
#iommu-cells = <0>;
status = "disabled";
};
vop: vop@20050000 {
compatible = "rockchip,rk322x-vop";
reg = <0x20050000 0x1ffc>;
reg-names = "regs";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
status = "disabled";
vop_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
};
vop_out_tve: endpoint@1 {
reg = <1>;
remote-endpoint = <&tve_in_vop>;
};
};
};
vop_mmu: iommu@20050300 {
compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
rk_rga: rk_rga@20060000 {
compatible = "rockchip,rga2";
reg = <0x20060000 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
dma-coherent;
status = "disabled";
};
iep: iep@20070000 {
compatible = "rockchip,iep";
iommu_enabled = <1>;
iommus = <&iep_mmu>;
reg = <0x20070000 0x800>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk_iep", "hclk_iep";
version = <3>;
allocator = <1>;
status = "disabled";
};
iep_mmu: iommu@20070800 {
compatible = "rockchip,iommu";
reg = <0x20070800 0x40>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
#iommu-cells = <0>;
status = "disabled";
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
};
hdmi: hdmi@200a0000 {
compatible = "rockchip,rk3228-dw-hdmi";
reg = <0x200a0000 0x20000>;
reg-io-width = <4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>,
<&cru SCLK_HDMI_CEC>;
clock-names = "isfr", "iahb", "cec";
pinctrl-names = "default";
pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
resets = <&cru SRST_HDMI_P>;
reset-names = "hdmi";
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
rockchip,grf = <&grf>;
status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_hdmi>;
};
};
};
};
tve: tve@20053e00 {
compatible = "rockchip,rk3328-tve";
reg = <0x20053e00 0x100>,
<0x12020000 0x10000>;
rockchip,saturation = <0x00305b46>;
rockchip,brightcontrast = <0x00009900>;
rockchip,adjtiming = <0xd6c00880>;
rockchip,lumafilter0 = <0x02ff0001>;
rockchip,lumafilter1 = <0xf40200fe>;
rockchip,lumafilter2 = <0xf332d910>;
rockchip,daclevel = <0x15>;
rockchip,dac1level = <0x7>;
nvmem-cells = <&tve_dac>;
nvmem-cell-names = "tve_dac_adj";
status = "disabled";
ports {
tve_in: port {
#address-cells = <1>;
#size-cells = <0>;
tve_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_tve>;
};
};
};
};
sdmmc: dwmmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "disabled";
};
sdio: dwmmc@30010000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30010000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
status = "disabled";
};
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <37500000>;
clock-freq-min-max = <400000 37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
bus-width = <8>;
default-sample-phase = <158>;
num-slots = <1>;
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "disabled";
};
nandc: nandc@30030000 {
compatible = "rockchip,rk-nandc";
reg = <0x30030000 0x4000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
nandc_id = <0>;
clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
clock-names = "clk_nandc", "hclk_nandc";
status = "disabled";
};
usb_otg: usb@30040000 {
compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x30040000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
g-use-dma;
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host0_ehci: usb@30080000 {
compatible = "generic-ehci";
reg = <0x30080000 0x20000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
clock-names = "usbhost", "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
};
usb_host0_ohci: usb@300a0000 {
compatible = "generic-ohci";
reg = <0x300a0000 0x20000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
clock-names = "usbhost", "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
};
usb_host1_ehci: usb@300c0000 {
compatible = "generic-ehci";
reg = <0x300c0000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
clock-names = "usbhost", "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
};
usb_host1_ohci: usb@300e0000 {
compatible = "generic-ohci";
reg = <0x300e0000 0x20000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
clock-names = "usbhost", "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
};
usb_host2_ehci: usb@30100000 {
compatible = "generic-ehci";
reg = <0x30100000 0x20000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
phys = <&u2phy1_otg>;
phy-names = "usb";
clock-names = "usbhost", "utmi";
status = "disabled";
};
usb_host2_ohci: usb@30120000 {
compatible = "generic-ohci";
reg = <0x30120000 0x20000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
clock-names = "usbhost", "utmi";
phys = <&u2phy1_otg>;
phy-names = "usb";
status = "disabled";
};
gmac: ethernet@30200000 {
compatible = "rockchip,rk3228-gmac";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac", "clk_macphy";
resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>;
reset-names = "stmmaceth", "mac-phy";
rockchip,grf = <&grf>;
status = "disabled";
};
qos_vpu: qos@31040000 {
compatible = "syscon";
reg = <0x31040000 0x20>;
};
qos_rkvdec_r: qos@31070000 {
compatible = "syscon";
reg = <0x31070000 0x20>;
};
qos_rkvdec_w: qos@31070080 {
compatible = "syscon";
reg = <0x31070080 0x20>;
};
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x32011000 0x1000>,
<0x32012000 0x2000>,
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3228-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@11110000 {
compatible = "rockchip,gpio-bank";
reg = <0x11110000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@11120000 {
compatible = "rockchip,gpio-bank";
reg = <0x11120000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@11130000 {
compatible = "rockchip,gpio-bank";
reg = <0x11130000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@11140000 {
compatible = "rockchip,gpio-bank";
reg = <0x11140000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
drive-strength = <12>;
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
<1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
};
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
<3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
<3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
<3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
<1 RK_PD1 2 &pcfg_pull_none>,
<1 RK_PD2 2 &pcfg_pull_none>,
<1 RK_PD3 2 &pcfg_pull_none>,
<1 RK_PD4 2 &pcfg_pull_none>,
<1 RK_PD5 2 &pcfg_pull_none>,
<1 RK_PD6 2 &pcfg_pull_none>,
<1 RK_PD7 2 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
<2 RK_PB4 1 &pcfg_pull_none>,
<2 RK_PD1 1 &pcfg_pull_none>,
<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC1 1 &pcfg_pull_none>,
<2 RK_PC0 1 &pcfg_pull_none>,
<2 RK_PC5 2 &pcfg_pull_none>,
<2 RK_PC4 2 &pcfg_pull_none>,
<2 RK_PB3 1 &pcfg_pull_none>,
<2 RK_PB0 1 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
<2 RK_PB4 1 &pcfg_pull_none>,
<2 RK_PD1 1 &pcfg_pull_none>,
<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
<2 RK_PC1 1 &pcfg_pull_none>,
<2 RK_PC0 1 &pcfg_pull_none>,
<2 RK_PB0 1 &pcfg_pull_none>,
<2 RK_PB7 1 &pcfg_pull_none>;
};
phy_pins: phy-pins {
rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
<2 RK_PB0 2 &pcfg_pull_none>;
};
};
hdmi {
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
};
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
<0 RK_PA7 2 &pcfg_pull_none>;
};
hdmi_cec: hdmi-cec {
rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
<0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
<0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
<2 RK_PC5 1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
<0 RK_PA7 1 &pcfg_pull_none>;
};
};
tsp {
tsp_d0: tsp-d0 {
rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
};
tsp_d1: tsp-d1 {
rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
};
tsp_d2: tsp-d2 {
rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
};
tsp_d3: tsp-d3 {
rockchip,pins = <2 RK_PC0 2 &pcfg_pull_none>;
};
tsp_d4: tsp-d4 {
rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
};
tsp_d5: tsp-d5 {
rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
};
tsp_d6: tsp-d6 {
rockchip,pins = <2 RK_PB7 2 &pcfg_pull_none>;
};
tsp_d7: tsp-d7 {
rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
};
tsp_sync: tsp-sync {
rockchip,pins = <2 RK_PB4 2 &pcfg_pull_none>;
};
tsp_clk: tsp-clk {
rockchip,pins = <2 RK_PB3 2 &pcfg_pull_none>;
};
tsp_fail: tsp-fail {
rockchip,pins = <2 RK_PB2 2 &pcfg_pull_none>;
};
tsp_valid: tsp-valid {
rockchip,pins = <2 RK_PB1 2 &pcfg_pull_none>;
};
};
spi-0 {
spi0_clk: spi0-clk {
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
};
};
spi-1 {
spi1_clk: spi1-clk {
rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
<0 RK_PB1 1 &pcfg_pull_none>,
<0 RK_PB3 1 &pcfg_pull_none>,
<0 RK_PB4 1 &pcfg_pull_none>,
<0 RK_PB5 1 &pcfg_pull_none>,
<0 RK_PB6 1 &pcfg_pull_none>,
<1 RK_PA2 2 &pcfg_pull_none>,
<1 RK_PA4 2 &pcfg_pull_none>,
<1 RK_PA5 2 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
};
pwm0_pin_pull_down: pwm0-pin-pull-down {
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_down>;
};
pwm0_pin_pull_down: pwm0-pin-pull-down {
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_down>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
};
pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
};
pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
};
pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins = <1 RK_PB4 2 &pcfg_pull_down>;
};
pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins = <1 RK_PB4 2 &pcfg_pull_down>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
};
pwm3_pin_pull_down: pwm3-pin-pull-down {
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_down>;
};
pwm3_pin_pull_down: pwm3-pin-pull-down {
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_down>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
<2 RK_PD3 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
<1 RK_PB2 1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
};
};
uart1-1 {
uart11_xfer: uart11-xfer {
rockchip,pins = <3 RK_PB6 1 &pcfg_pull_up>,
<3 RK_PB5 1 &pcfg_pull_none>;
};
uart11_cts: uart11-cts {
rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
};
uart11_rts: uart11-rts {
rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
};
uart11_rts_gpio: uart11-rts-gpio {
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
<1 RK_PC3 2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
};
uart2_rts: uart2-rts {
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
};
};
uart2-1 {
uart21_xfer: uart21-xfer {
rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
<1 RK_PB1 2 &pcfg_pull_none>;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk322x";
status = "disabled";
rockchip,virtual-poweroff = <0>;
rockchip,sleep-mode-config = <
(0
|RKPM_CTR_GTCLKS
|RKPM_CTR_IDLESRAM_MD
)
>;
};
};