96 lines
1.3 KiB
Plaintext
96 lines
1.3 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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/dts-v1/;
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#include "rk3288-evb-rk628.dtsi"
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&sound {
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status = "okay";
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};
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&rk628_hdmi {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi_in_post_process: endpoint {
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remote-endpoint = <&post_process_out_hdmi>;
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};
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};
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};
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};
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&rk628_post_process {
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pinctrl-names = "default";
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pinctrl-0 = <&rk628_vop_pins>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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post_process_in_rgb: endpoint {
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remote-endpoint = <&rgb_out_post_process>;
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};
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};
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port@1 {
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reg = <1>;
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post_process_out_hdmi: endpoint {
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remote-endpoint = <&hdmi_in_post_process>;
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};
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};
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};
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};
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&rgb {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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rgb_out_post_process: endpoint {
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remote-endpoint = <&post_process_in_rgb>;
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};
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};
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};
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};
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&video_phy {
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status = "okay";
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};
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&rgb_in_vopb {
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status = "disabled";
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};
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&rgb_in_vopl {
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status = "okay";
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};
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&route_rgb {
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connect = <&vopl_out_rgb>;
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status = "disabled";
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};
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&vopb {
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assigned-clocks = <&cru DCLK_VOP0>;
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assigned-clock-parents = <&cru PLL_CPLL>;
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};
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&vopl {
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assigned-clocks = <&cru DCLK_VOP1>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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