108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef LS_DEF_H
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#define LS_DEF_H
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#include <platform_def.h>
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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/******************************************************************************
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* Definitions common to all ARM standard platforms
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*****************************************************************************/
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define LS_CACHE_WRITEBACK_SHIFT 6
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/*
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* Macros mapping the MPIDR Affinity levels to Layerscape Platform Power levels. The
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* power levels have a 1:1 mapping with the MPIDR affinity levels.
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*/
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#define LS_PWR_LVL0 MPIDR_AFFLVL0
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#define LS_PWR_LVL1 MPIDR_AFFLVL1
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#define LS_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in Layerscape platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define LS_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define LS_LOCAL_STATE_RET U(1)
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains
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*/
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#define LS_LOCAL_STATE_OFF U(2)
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#define LS_MAP_NS_DRAM MAP_REGION_FLAT( \
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(LS_NS_DRAM_BASE), \
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LS_DRAM1_SIZE, \
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MT_DEVICE | MT_RW | MT_NS)
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#define LS_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
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TSP_SEC_MEM_BASE, \
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TSP_SEC_MEM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define LS_MAP_FLASH0_RW MAP_REGION_FLAT(PLAT_LS_FLASH_BASE,\
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PLAT_LS_FLASH_SIZE, \
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MT_DEVICE | MT_RW)
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#define LS_MAP_CCSR MAP_REGION_FLAT(PLAT_LS_CCSR_BASE, \
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PLAT_LS_CCSR_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define LS_MAP_CONSOLE MAP_REGION_FLAT(PLAT_LS1043_DUART1_BASE, \
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PLAT_LS1043_DUART_SIZE, \
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MT_DEVICE | MT_RW | MT_NS)
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/*
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* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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/******************************************************************************
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* Required platform porting definitions common to all ARM standard platforms
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*****************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE LS_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE LS_LOCAL_STATE_OFF
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << LS_CACHE_WRITEBACK_SHIFT)
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/*
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* One cache line needed for bakery locks on Layerscape platforms
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*/
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#endif /* LS_DEF_H */
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