79 lines
2.3 KiB
C
79 lines
2.3 KiB
C
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv2.h>
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#include "ls_16550.h"
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#include "plat_ls.h"
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#include "soc.h"
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static const interrupt_prop_t g0_interrupt_props[] = {
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INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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};
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gicv2_driver_data_t ls_gic_data = {
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.gicd_base = GICD_BASE,
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.gicc_base = GICC_BASE,
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.interrupt_props = g0_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
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};
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/*******************************************************************************
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* Initialize the UART
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******************************************************************************/
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void ls_tsp_early_platform_setup(void)
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{
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static console_t console;
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/*
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* Initialize a different console than already in use to display
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* messages from TSP
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*/
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console_ls_16550_register(PLAT_LS1043_UART2_BASE, PLAT_LS1043_UART_CLOCK,
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PLAT_LS1043_UART_BAUDRATE, &console);
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NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL32);
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}
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/*******************************************************************************
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* Perform platform specific setup placeholder
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******************************************************************************/
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void tsp_platform_setup(void)
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{
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uint32_t gicc_base, gicd_base;
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/* Initialize the GIC driver, cpu and distributor interfaces */
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get_gic_offset(&gicc_base, &gicd_base);
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ls_gic_data.gicd_base = (uintptr_t)gicd_base;
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ls_gic_data.gicc_base = (uintptr_t)gicc_base;
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gicv2_driver_init(&ls_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the MMU
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******************************************************************************/
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void tsp_plat_arch_setup(void)
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{
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ls_setup_page_tables(BL32_BASE,
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(BL32_END - BL32_BASE),
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el1(0);
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}
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