322 lines
13 KiB
C
322 lines
13 KiB
C
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <drivers/arm/gic_common.h>
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#define PLAT_PRIMARY_CPU 0x0
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#define IO_PHYS 0x10000000
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define PERI_BASE (IO_PHYS + 0x3000)
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#define GPIO_BASE (IO_PHYS + 0x5000)
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#define SPM_BASE (IO_PHYS + 0x6000)
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#define SLEEP_REG_MD_BASE (IO_PHYS + 0xf000)
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#define RGU_BASE (IO_PHYS + 0x7000)
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#define I2C4_BASE_SE (IO_PHYS + 0x1008000)
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#define I2C2_BASE_SE (IO_PHYS + 0x1009000)
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#define PMIC_WRAP_BASE (IO_PHYS + 0xd000)
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#define MCUCFG_BASE 0x0c530000
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#define CFG_SF_CTRL 0x0c510014
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#define CFG_SF_INI 0x0c510010
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#define EMI_BASE (IO_PHYS + 0x219000)
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#define EMI_MPU_BASE (IO_PHYS + 0x226000)
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#define TRNG_base (IO_PHYS + 0x20f000)
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#define MT_GIC_BASE 0x0c000000
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#define PLAT_MT_CCI_BASE 0x0c500000
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#define CCI_SIZE 0x00010000
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#define EINT_BASE 0x1000b000
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#define DVFSRC_BASE (IO_PHYS + 0x12000)
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#define SSPM_CFGREG_BASE (IO_PHYS + 0x440000)
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#define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000)
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define TOPCKGEN_BASE (IO_PHYS + 0x0)
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#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
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#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204)
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#define APMIXEDSYS (IO_PHYS + 0xC000)
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#define AP_PLL_CON3 (APMIXEDSYS + 0xC)
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#define AP_PLL_CON4 (APMIXEDSYS + 0x10)
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#define AP_PLL_CON6 (APMIXEDSYS + 0x18)
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#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200)
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#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210)
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#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c)
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#define MAINPLL_CON0 (APMIXEDSYS + 0x220)
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#define CCIPLL_CON0 (APMIXEDSYS + 0x290)
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#define TOP_CKMUXSEL (INFRACFG_AO_BASE + 0x0)
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#define armpll_mux1_sel_big_mask (0xf << 4)
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#define armpll_mux1_sel_big_ARMSPLL (0x1 << 4)
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#define armpll_mux1_sel_sml_mask (0xf << 8)
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#define armpll_mux1_sel_sml_ARMSPLL (0x1 << 8)
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/* Aggregate of all devices in the first GB */
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#define MTK_DEV_RNG0_BASE IO_PHYS
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#define MTK_DEV_RNG0_SIZE 0x490000
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#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
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#define MTK_DEV_RNG1_SIZE 0x4000000
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#define MTK_DEV_RNG2_BASE 0x0c000000
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#define MTK_DEV_RNG2_SIZE 0x600000
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#define MT_MCUSYS_SIZE 0x90000
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#define RAM_CONSOLE_BASE 0x11d000
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#define RAM_CONSOLE_SIZE 0x1000
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/*******************************************************************************
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* MSDC
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******************************************************************************/
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#define MSDC0_BASE (IO_PHYS + 0x01230000)
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/*******************************************************************************
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* MCUSYS related constants
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******************************************************************************/
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#define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604)
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#define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0)
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#define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4)
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#define EMI_WFIFO (MCUCFG_BASE + 0x0b5c)
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define MT_POLARITY_LOW 0
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#define MT_POLARITY_HIGH 1
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#define MT_EDGE_SENSITIVE 1
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#define MT_LEVEL_SENSITIVE 0
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define UART0_BASE (IO_PHYS + 0x01002000)
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#define UART1_BASE (IO_PHYS + 0x01003000)
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#define UART_BAUDRATE 115200
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#define UART_CLOCK 26000000
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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#define SYS_COUNTER_FREQ_IN_MHZ 13
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE MT_GIC_BASE
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#define BASE_GICC_BASE (MT_GIC_BASE + 0x400000)
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#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x100000)
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#define BASE_GICR_BASE (MT_GIC_BASE + 0x100000)
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#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
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#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
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#define INT_POL_CTL0 (MCUCFG_BASE + 0xa80)
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#define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00)
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#define GIC_SYNC_DCM (MCUCFG_BASE + 0x758)
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#define GIC_SYNC_DCM_MASK 0x3
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#define GIC_SYNC_DCM_ON 0x3
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#define GIC_SYNC_DCM_OFF 0x0
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#define GIC_PRIVATE_SIGNALS 32
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) ( \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)) \
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#define PLAT_ARM_G0_IRQ_PROPS(grp)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
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/*******************************************************************************
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* WDT Registers
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******************************************************************************/
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#define MTK_WDT_BASE (IO_PHYS + 0x00007000)
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#define MTK_WDT_SIZE 0x1000
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#define MTK_WDT_MODE (MTK_WDT_BASE + 0x0000)
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#define MTK_WDT_LENGTH (MTK_WDT_BASE + 0x0004)
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#define MTK_WDT_RESTART (MTK_WDT_BASE + 0x0008)
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#define MTK_WDT_STATUS (MTK_WDT_BASE + 0x000C)
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#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x0010)
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#define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014)
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#define MTK_WDT_SWSYSRST (MTK_WDT_BASE + 0x0018)
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#define MTK_WDT_NONRST_REG (MTK_WDT_BASE + 0x0020)
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#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE + 0x0024)
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#define MTK_WDT_REQ_MODE (MTK_WDT_BASE + 0x0030)
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#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE + 0x0034)
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#define MTK_WDT_EXT_REQ_CON (MTK_WDT_BASE + 0x0038)
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#define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE + 0x0040)
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#define MTK_WDT_LATCH_CTL (MTK_WDT_BASE + 0x0044)
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#define MTK_WDT_DEBUG_CTL2 (MTK_WDT_BASE + 0x00A0)
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#define MTK_WDT_COUNTER (MTK_WDT_BASE + 0x0514)
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/* WDT_STATUS */
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#define MTK_WDT_STATUS_SPM_THERMAL_RST (1 << 0)
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#define MTK_WDT_STATUS_SPM_RST (1 << 1)
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#define MTK_WDT_STATUS_EINT_RST (1 << 2)
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#define MTK_WDT_STATUS_SYSRST_RST (1 << 3) /* from PMIC */
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#define MTK_WDT_STATUS_DVFSP_RST (1 << 4)
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#define MTK_WDT_STATUS_PMCU_RST (1 << 16)
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#define MTK_WDT_STATUS_MDDBG_RST (1 << 17)
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#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1 << 18)
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#define MTK_WDT_STATUS_DEBUG_RST (1 << 19)
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#define MTK_WDT_STATUS_SECURITY_RST (1 << 28)
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#define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29)
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#define MTK_WDT_STATUS_SW_WDT_RST (1 << 30)
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#define MTK_WDT_STATUS_HW_WDT_RST (1U << 31)
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/* RGU other related */
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#define MTK_WDT_MODE_DUAL_MODE 0x0040
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#define MTK_WDT_MODE_IRQ 0x0008
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#define MTK_WDT_MODE_KEY 0x22000000
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#define MTK_WDT_MODE_EXTEN 0x0004
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#define MTK_WDT_SWRST_KEY 0x1209
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#define MTK_WDT_RESTART_KEY 0x1971
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/*******************************************************************************
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* TRNG Registers
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******************************************************************************/
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#define TRNG_BASE_ADDR TRNG_base
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#define TRNG_BASE_SIZE 0x1000
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#define TRNG_CTRL (TRNG_base + 0x0000)
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#define TRNG_TIME (TRNG_base + 0x0004)
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#define TRNG_DATA (TRNG_base + 0x0008)
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#define TRNG_PDN_base 0x10001000
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#define TRNG_PDN_BASE_ADDR TRNG_PDN_BASE_ADDR
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#define TRNG_PDN_BASE_SIZE 0x1000
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#define TRNG_PDN_SET (TRNG_PDN_base + 0x0088)
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#define TRNG_PDN_CLR (TRNG_PDN_base + 0x008c)
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#define TRNG_PDN_STATUS (TRNG_PDN_base + 0x0094)
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#define TRNG_CTRL_RDY 0x80000000
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#define TRNG_CTRL_START 0x00000001
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#define TRNG_PDN_VALUE 0x200
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/* FIQ platform related define */
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#define MT_IRQ_SEC_SGI_0 8
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#define MT_IRQ_SEC_SGI_1 9
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#define MT_IRQ_SEC_SGI_2 10
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#define MT_IRQ_SEC_SGI_3 11
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#define MT_IRQ_SEC_SGI_4 12
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#define MT_IRQ_SEC_SGI_5 13
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#define MT_IRQ_SEC_SGI_6 14
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#define MT_IRQ_SEC_SGI_7 15
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#define FIQ_SMP_CALL_SGI 13
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#define WDT_IRQ_BIT_ID 174
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#define ATF_LOG_IRQ_ID 277
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#define ATF_AMMS_IRQ_ID 338
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#define PCCIF1_IRQ0_BIT_ID 185
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#define PCCIF1_IRQ1_BIT_ID 186
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#define DEBUG_XLAT_TABLE 0
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if DEBUG_XLAT_TABLE
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#define PLATFORM_STACK_SIZE 0x800
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#elif IMAGE_BL1
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#define PLATFORM_STACK_SIZE 0x440
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#elif IMAGE_BL2
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#define PLATFORM_STACK_SIZE 0x400
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#elif IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#elif IMAGE_BL32
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#define PLATFORM_STACK_SIZE 0x440
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#endif
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define SOC_CHIP_ID U(0x8183)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZRAM_BASE 0x54600000
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#define TZRAM_SIZE 0x00030000
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + 0x1000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 16
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* PLATFORM_DEF_H */
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