132 lines
4.2 KiB
C
132 lines
4.2 KiB
C
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/**
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******************************************************************************
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*
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* @file rwnx_platorm.h
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*
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* Copyright (C) RivieraWaves 2012-2019
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*
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******************************************************************************
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*/
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#ifndef _RWNX_PLATFORM_H_
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#define _RWNX_PLATFORM_H_
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#include <linux/pci.h>
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#include "lmac_msg.h"
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#define RWNX_CONFIG_FW_NAME "rwnx_settings.ini"
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#define RWNX_PHY_CONFIG_TRD_NAME "rwnx_trident.ini"
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#define RWNX_PHY_CONFIG_KARST_NAME "rwnx_karst.ini"
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#define RWNX_AGC_FW_NAME "agcram.bin"
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#define RWNX_LDPC_RAM_NAME "ldpcram.bin"
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#ifdef CONFIG_RWNX_FULLMAC
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#define RWNX_MAC_FW_BASE_NAME "fmacfw"
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#elif defined CONFIG_RWNX_FHOST
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#define RWNX_MAC_FW_BASE_NAME "fhostfw"
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#endif /* CONFIG_RWNX_FULLMAC */
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#ifdef CONFIG_RWNX_TL4
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#define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME".hex"
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#else
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#define RWNX_MAC_FW_NAME RWNX_MAC_FW_BASE_NAME".ihex"
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#define RWNX_MAC_FW_NAME2 RWNX_MAC_FW_BASE_NAME".bin"
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#endif
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#define RWNX_FCU_FW_NAME "fcuram.bin"
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/**
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* Type of memory to access (cf rwnx_plat.get_address)
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*
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* @RWNX_ADDR_CPU To access memory of the embedded CPU
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* @RWNX_ADDR_SYSTEM To access memory/registers of one subsystem of the
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* embedded system
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*
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*/
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enum rwnx_platform_addr {
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RWNX_ADDR_CPU,
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RWNX_ADDR_SYSTEM,
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RWNX_ADDR_MAX,
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};
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struct rwnx_hw;
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/**
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* struct rwnx_plat - Operation pointers for RWNX PCI platform
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*
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* @pci_dev: pointer to pci dev
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* @enabled: Set if embedded platform has been enabled (i.e. fw loaded and
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* ipc started)
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* @enable: Configure communication with the fw (i.e. configure the transfers
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* enable and register interrupt)
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* @disable: Stop communication with the fw
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* @deinit: Free all ressources allocated for the embedded platform
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* @get_address: Return the virtual address to access the requested address on
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* the platform.
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* @ack_irq: Acknowledge the irq at link level.
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* @get_config_reg: Return the list (size + pointer) of registers to restore in
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* order to reload the platform while keeping the current configuration.
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*
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* @priv Private data for the link driver
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*/
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struct rwnx_plat {
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struct pci_dev *pci_dev;
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#ifdef AICWF_SDIO_SUPPORT
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struct aic_sdio_dev *sdiodev;
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#endif
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#ifdef AICWF_USB_SUPPORT
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struct aic_usb_dev *usbdev;
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#endif
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bool enabled;
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int (*enable)(struct rwnx_hw *rwnx_hw);
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int (*disable)(struct rwnx_hw *rwnx_hw);
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void (*deinit)(struct rwnx_plat *rwnx_plat);
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u8* (*get_address)(struct rwnx_plat *rwnx_plat, int addr_name,
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unsigned int offset);
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void (*ack_irq)(struct rwnx_plat *rwnx_plat);
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int (*get_config_reg)(struct rwnx_plat *rwnx_plat, const u32 **list);
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u8 priv[0] __aligned(sizeof(void *));
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};
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#define RWNX_ADDR(plat, base, offset) \
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plat->get_address(plat, base, offset)
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#define RWNX_REG_READ(plat, base, offset) \
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readl(plat->get_address(plat, base, offset))
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#define RWNX_REG_WRITE(val, plat, base, offset) \
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writel(val, plat->get_address(plat, base, offset))
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extern struct rwnx_plat *g_rwnx_plat;
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int rwnx_platform_init(struct rwnx_plat *rwnx_plat, void **platform_data);
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void rwnx_platform_deinit(struct rwnx_hw *rwnx_hw);
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int rwnx_platform_on(struct rwnx_hw *rwnx_hw, void *config);
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void rwnx_platform_off(struct rwnx_hw *rwnx_hw, void **config);
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int rwnx_platform_register_drv(void);
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void rwnx_platform_unregister_drv(void);
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void get_userconfig_txpwr_idx(txpwr_idx_conf_t *txpwr_idx);
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void get_userconfig_txpwr_ofst(txpwr_ofst_conf_t *txpwr_ofst);
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void get_userconfig_xtal_cap(xtal_cap_conf_t *xtal_cap);
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void get_userconfig_txpwr_lvl_in_fdrv(txpwr_lvl_conf_t *txpwr_lvl);
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void get_userconfig_txpwr_lvl_v2_in_fdrv(txpwr_lvl_conf_v2_t *txpwr_lvl_v2);
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void get_userconfig_txpwr_lvl_v3_in_fdrv(txpwr_lvl_conf_v3_t *txpwr_lvl_v3);
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void get_userconfig_txpwr_ofst_in_fdrv(txpwr_ofst_conf_t *txpwr_ofst);
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extern struct device *rwnx_platform_get_dev(struct rwnx_plat *rwnx_plat);
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static inline unsigned int rwnx_platform_get_irq(struct rwnx_plat *rwnx_plat)
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{
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return rwnx_plat->pci_dev->irq;
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}
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#endif /* _RWNX_PLATFORM_H_ */
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