403 lines
15 KiB
C
403 lines
15 KiB
C
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/**
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****************************************************************************************
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*
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* @file rwnx_txq.h
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*
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* Copyright (C) RivieraWaves 2012-2019
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*
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****************************************************************************************
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*/
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#ifndef _RWNX_TXQ_H_
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#define _RWNX_TXQ_H_
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/ieee80211.h>
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#ifdef CONFIG_RWNX_FULLMAC
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/**
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* Fullmac TXQ configuration:
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* - STA: 1 TXQ per TID (limited to 8)
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* 1 TXQ for bufferable MGT frames
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* - VIF: 1 TXQ for Multi/Broadcast +
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* 1 TXQ for MGT for unknown STAs or non-bufferable MGT frames
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* - 1 TXQ for offchannel transmissions
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*
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*
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* Txq mapping looks like
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* for NX_REMOTE_STA_MAX=10 and NX_VIRT_DEV_MAX=4
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*
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* | TXQ | NDEV_ID | VIF | STA | TID | HWQ |
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* |-----+---------+-----+-------+------+-----|-
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* | 0 | 0 | | 0 | 0 | 1 | 9 TXQ per STA
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* | 1 | 1 | | 0 | 1 | 0 | (8 data + 1 mgmt)
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* | 2 | 2 | | 0 | 2 | 0 |
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* | 3 | 3 | | 0 | 3 | 1 |
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* | 4 | 4 | | 0 | 4 | 2 |
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* | 5 | 5 | | 0 | 5 | 2 |
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* | 6 | 6 | | 0 | 6 | 3 |
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* | 7 | 7 | | 0 | 7 | 3 |
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* | 8 | N/A | | 0 | MGMT | 3 |
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* |-----+---------+-----+-------+------+-----|-
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* | ... | | | | | | Same for all STAs
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* |-----+---------+-----+-------+------+-----|-
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* | 90 | 80 | 0 | BC/MC | 0 | 1/4 | 1 TXQ for BC/MC per VIF
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* | ... | | | | | |
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* | 93 | 80 | 3 | BC/MC | 0 | 1/4 |
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* |-----+---------+-----+-------+------+-----|-
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* | 94 | N/A | 0 | N/A | MGMT | 3 | 1 TXQ for unknown STA per VIF
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* | ... | | | | | |
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* | 97 | N/A | 3 | N/A | MGMT | 3 |
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* |-----+---------+-----+-------+------+-----|-
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* | 98 | N/A | | N/A | MGMT | 3 | 1 TXQ for offchannel frame
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*/
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#define NX_NB_TID_PER_STA 8
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#define NX_NB_TXQ_PER_STA (NX_NB_TID_PER_STA + 1)
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#define NX_NB_TXQ_PER_VIF 2
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#define NX_NB_TXQ ((NX_NB_TXQ_PER_STA * NX_REMOTE_STA_MAX) + \
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(NX_NB_TXQ_PER_VIF * NX_VIRT_DEV_MAX) + 1)
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#define NX_FIRST_VIF_TXQ_IDX (NX_REMOTE_STA_MAX * NX_NB_TXQ_PER_STA)
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#define NX_FIRST_BCMC_TXQ_IDX NX_FIRST_VIF_TXQ_IDX
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#define NX_FIRST_UNK_TXQ_IDX (NX_FIRST_BCMC_TXQ_IDX + NX_VIRT_DEV_MAX)
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#define NX_OFF_CHAN_TXQ_IDX (NX_FIRST_VIF_TXQ_IDX + \
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(NX_VIRT_DEV_MAX * NX_NB_TXQ_PER_VIF))
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#define NX_FIRST_VIF_TXQ_IDX_FOR_OLD_IC (NX_REMOTE_STA_MAX_FOR_OLD_IC * NX_NB_TXQ_PER_STA)
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#define NX_FIRST_BCMC_TXQ_IDX_FOR_OLD_IC NX_FIRST_VIF_TXQ_IDX_FOR_OLD_IC
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#define NX_FIRST_UNK_TXQ_IDX_FOR_OLD_IC (NX_FIRST_BCMC_TXQ_IDX_FOR_OLD_IC + NX_VIRT_DEV_MAX)
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#define NX_OFF_CHAN_TXQ_IDX_FOR_OLD_IC (NX_FIRST_VIF_TXQ_IDX_FOR_OLD_IC + \
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(NX_VIRT_DEV_MAX * NX_NB_TXQ_PER_VIF))
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#define NX_BCMC_TXQ_TYPE 0
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#define NX_UNK_TXQ_TYPE 1
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/**
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* Each data TXQ is a netdev queue. TXQ to send MGT are not data TXQ as
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* they did not recieved buffer from netdev interface.
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* Need to allocate the maximum case.
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* AP : all STAs + 1 BC/MC
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*/
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#define NX_NB_NDEV_TXQ ((NX_NB_TID_PER_STA * NX_REMOTE_STA_MAX) + 1)
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#define NX_NB_NDEV_TXQ_FOR_OLD_IC ((NX_NB_TID_PER_STA * NX_REMOTE_STA_MAX_FOR_OLD_IC) + 1)
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#define NX_BCMC_TXQ_NDEV_IDX (NX_NB_TID_PER_STA * NX_REMOTE_STA_MAX)
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#define NX_BCMC_TXQ_NDEV_IDX_FOR_OLD_IC (NX_NB_TID_PER_STA * NX_REMOTE_STA_MAX_FOR_OLD_IC)
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#define NX_STA_NDEV_IDX(tid, sta_idx) ((tid) + (sta_idx) * NX_NB_TID_PER_STA)
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#define NDEV_NO_TXQ 0xffff
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#if (NX_NB_NDEV_TXQ >= NDEV_NO_TXQ)
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#error("Need to increase struct rwnx_txq->ndev_idx size")
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#endif
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/* stop netdev queue when number of queued buffers if greater than this */
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#define RWNX_NDEV_FLOW_CTRL_STOP 64
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/* restart netdev queue when number of queued buffers is lower than this */
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#define RWNX_NDEV_FLOW_CTRL_RESTART 64
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#endif /* CONFIG_RWNX_FULLMAC */
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#define TXQ_INACTIVE 0xffff
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#if (NX_NB_TXQ >= TXQ_INACTIVE)
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#error("Need to increase struct rwnx_txq->idx size")
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#endif
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#define NX_TXQ_INITIAL_CREDITS 64
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/**
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* TXQ tid sorted by decreasing priority
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*/
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extern const int nx_tid_prio[NX_NB_TID_PER_STA];
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/**
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* struct rwnx_hwq - Structure used to save information relative to
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* an AC TX queue (aka HW queue)
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* @list: List of TXQ, that have buffers ready for this HWQ
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* @credits: available credit for the queue (i.e. nb of buffers that
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* can be pushed to FW )
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* @id Id of the HWQ among RWNX_HWQ_....
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* @size size of the queue
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* @need_processing Indicate if hwq should be processed
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* @len number of packet ready to be pushed to fw for this HW queue
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* @len_stop threshold to stop mac80211(i.e. netdev) queues. Stop queue when
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* driver has more than @len_stop packets ready.
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* @len_start threshold to wake mac8011 queues. Wake queue when driver has
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* less than @len_start packets ready.
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*/
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struct rwnx_hwq {
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struct list_head list;
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u8 size;
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u8 id;
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bool need_processing;
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};
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/**
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* enum rwnx_push_flags - Flags of pushed buffer
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*
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* @RWNX_PUSH_RETRY Pushing a buffer for retry
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* @RWNX_PUSH_IMMEDIATE Pushing a buffer without queuing it first
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*/
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enum rwnx_push_flags {
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RWNX_PUSH_RETRY = BIT(0),
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RWNX_PUSH_IMMEDIATE = BIT(1),
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};
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/**
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* enum rwnx_txq_flags - TXQ status flag
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*
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* @RWNX_TXQ_IN_HWQ_LIST: The queue is scheduled for transmission
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* @RWNX_TXQ_STOP_FULL: No more credits for the queue
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* @RWNX_TXQ_STOP_CSA: CSA is in progress
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* @RWNX_TXQ_STOP_STA_PS: Destiniation sta is currently in power save mode
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* @RWNX_TXQ_STOP_VIF_PS: Vif owning this queue is currently in power save mode
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* @RWNX_TXQ_STOP_CHAN: Channel of this queue is not the current active channel
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* @RWNX_TXQ_STOP_MU_POS: TXQ is stopped waiting for all the buffers pushed to
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* fw to be confirmed
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* @RWNX_TXQ_STOP: All possible reason to have a txq stopped
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* @RWNX_TXQ_NDEV_FLOW_CTRL: associated netdev queue is currently stopped.
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* Note: when a TXQ is flowctrl it is NOT stopped
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*/
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enum rwnx_txq_flags {
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RWNX_TXQ_IN_HWQ_LIST = BIT(0),
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RWNX_TXQ_STOP_FULL = BIT(1),
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RWNX_TXQ_STOP_CSA = BIT(2),
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RWNX_TXQ_STOP_STA_PS = BIT(3),
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RWNX_TXQ_STOP_VIF_PS = BIT(4),
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RWNX_TXQ_STOP_CHAN = BIT(5),
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RWNX_TXQ_STOP_MU_POS = BIT(6),
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RWNX_TXQ_STOP = (RWNX_TXQ_STOP_FULL | RWNX_TXQ_STOP_CSA |
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RWNX_TXQ_STOP_STA_PS | RWNX_TXQ_STOP_VIF_PS |
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RWNX_TXQ_STOP_CHAN),
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RWNX_TXQ_NDEV_FLOW_CTRL = BIT(7),
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};
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/**
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* struct rwnx_txq - Structure used to save information relative to
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* a RA/TID TX queue
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*
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* @idx: Unique txq idx. Set to TXQ_INACTIVE if txq is not used.
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* @status: bitfield of @rwnx_txq_flags.
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* @credits: available credit for the queue (i.e. nb of buffers that
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* can be pushed to FW).
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* @pkt_sent: number of consecutive pkt sent without leaving HW queue list
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* @pkt_pushed: number of pkt currently pending for transmission confirmation
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* @sched_list: list node for HW queue schedule list (rwnx_hwq.list)
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* @sk_list: list of buffers to push to fw
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* @last_retry_skb: pointer on the last skb in @sk_list that is a retry.
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* (retry skb are stored at the beginning of the list)
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* NULL if no retry skb is queued in @sk_list
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* @nb_retry: Number of retry packet queued.
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* @hwq: Pointer on the associated HW queue.
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* @push_limit: number of packet to push before removing the txq from hwq list.
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* (we always have push_limit < skb_queue_len(sk_list))
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* @tid: TID
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*
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* SOFTMAC specific:
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* @baw: Block Ack window information
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* @amsdu_anchor: pointer to rwnx_sw_txhdr of the first subframe of the A-MSDU.
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* NULL if no A-MSDU frame is in construction
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* @amsdu_ht_len_cap:
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* @amsdu_vht_len_cap:
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* @nb_ready_mac80211: Number of buffer ready in mac80211 txq
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*
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* FULLMAC specific
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* @ps_id: Index to use for Power save mode (LEGACY or UAPSD)
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* @ndev_idx: txq idx from netdev point of view (0xFF for non netdev queue)
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* @ndev: pointer to ndev of the corresponding vif
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* @amsdu: pointer to rwnx_sw_txhdr of the first subframe of the A-MSDU.
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* NULL if no A-MSDU frame is in construction
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* @amsdu_len: Maximum size allowed for an A-MSDU. 0 means A-MSDU not allowed
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*/
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struct rwnx_txq {
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u16 idx;
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u8 status;
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s8 credits;
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u8 pkt_sent;
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u8 pkt_pushed[CONFIG_USER_MAX];
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struct list_head sched_list;
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struct sk_buff_head sk_list;
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struct sk_buff *last_retry_skb;
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struct rwnx_hwq *hwq;
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int nb_retry;
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u8 push_limit;
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u8 tid;
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#ifdef CONFIG_MAC80211_TXQ
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unsigned long nb_ready_mac80211;
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#endif
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#ifdef CONFIG_RWNX_FULLMAC
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struct rwnx_sta *sta;
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u8 ps_id;
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u16 ndev_idx;
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struct net_device *ndev;
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#ifdef CONFIG_RWNX_AMSDUS_TX
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struct rwnx_sw_txhdr *amsdu;
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u16 amsdu_len;
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#endif /* CONFIG_RWNX_AMSDUS_TX */
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#endif /* CONFIG_RWNX_FULLMAC */
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#ifdef CONFIG_RWNX_MUMIMO_TX
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u8 mumimo_info;
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#endif
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};
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struct rwnx_sta;
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struct rwnx_vif;
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struct rwnx_hw;
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struct rwnx_sw_txhdr;
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#ifdef CONFIG_RWNX_MUMIMO_TX
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#define RWNX_TXQ_GROUP_ID(txq) ((txq)->mumimo_info & 0x3f)
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#define RWNX_TXQ_POS_ID(txq) (((txq)->mumimo_info >> 6) & 0x3)
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#else
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#define RWNX_TXQ_GROUP_ID(txq) 0
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#define RWNX_TXQ_POS_ID(txq) 0
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#endif /* CONFIG_RWNX_MUMIMO_TX */
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static inline bool rwnx_txq_is_stopped(struct rwnx_txq *txq)
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{
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return (txq->status & RWNX_TXQ_STOP);
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}
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static inline bool rwnx_txq_is_full(struct rwnx_txq *txq)
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{
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return (txq->status & RWNX_TXQ_STOP_FULL);
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}
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static inline bool rwnx_txq_is_scheduled(struct rwnx_txq *txq)
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{
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return (txq->status & RWNX_TXQ_IN_HWQ_LIST);
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}
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/**
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* foreach_sta_txq - Macro to iterate over all TXQ of a STA in increasing
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* TID order
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*
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* @sta: pointer to rwnx_sta
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* @txq: pointer to rwnx_txq updated with the next TXQ at each iteration
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* @tid: int updated with the TXQ tid at each iteration
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* @rwnx_hw: main driver data
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*/
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#ifdef CONFIG_MAC80211_TXQ
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#define foreach_sta_txq(sta, txq, tid, rwnx_hw) \
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for (tid = 0, txq = rwnx_txq_sta_get(sta, 0); \
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tid < NX_NB_TXQ_PER_STA; \
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tid++, txq = rwnx_txq_sta_get(sta, tid))
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#elif defined(CONFIG_RWNX_FULLMAC) /* CONFIG_RWNX_FULLMAC */
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#define foreach_sta_txq(sta, txq, tid, rwnx_hw) \
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for (tid = 0, txq = rwnx_txq_sta_get(sta, 0, rwnx_hw); \
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tid < (is_multicast_sta(sta->sta_idx) ? 1 : NX_NB_TXQ_PER_STA); \
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tid++, txq++)
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#endif
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/**
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* foreach_sta_txq_prio - Macro to iterate over all TXQ of a STA in
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* decreasing priority order
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*
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* @sta: pointer to rwnx_sta
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* @txq: pointer to rwnx_txq updated with the next TXQ at each iteration
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* @tid: int updated with the TXQ tid at each iteration
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* @i: int updated with ieration count
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* @rwnx_hw: main driver data
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*
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* Note: For fullmac txq for mgmt frame is skipped
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*/
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#ifdef CONFIG_RWNX_FULLMAC
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#define foreach_sta_txq_prio(sta, txq, tid, i, rwnx_hw) \
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|
for (i = 0, tid = nx_tid_prio[0], txq = rwnx_txq_sta_get(sta, tid, rwnx_hw); \
|
||
|
|
i < NX_NB_TID_PER_STA; \
|
||
|
|
i++, tid = nx_tid_prio[i], txq = rwnx_txq_sta_get(sta, tid, rwnx_hw))
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/**
|
||
|
|
* foreach_vif_txq - Macro to iterate over all TXQ of a VIF (in AC order)
|
||
|
|
*
|
||
|
|
* @vif: pointer to rwnx_vif
|
||
|
|
* @txq: pointer to rwnx_txq updated with the next TXQ at each iteration
|
||
|
|
* @ac: int updated with the TXQ ac at each iteration
|
||
|
|
*/
|
||
|
|
#ifdef CONFIG_MAC80211_TXQ
|
||
|
|
#define foreach_vif_txq(vif, txq, ac) \
|
||
|
|
for (ac = RWNX_HWQ_BK, txq = rwnx_txq_vif_get(vif, ac); \
|
||
|
|
ac < NX_NB_TXQ_PER_VIF; \
|
||
|
|
ac++, txq = rwnx_txq_vif_get(vif, ac))
|
||
|
|
|
||
|
|
#else
|
||
|
|
#define foreach_vif_txq(vif, txq, ac) \
|
||
|
|
for (ac = RWNX_HWQ_BK, txq = &vif->txqs[0]; \
|
||
|
|
ac < NX_NB_TXQ_PER_VIF; \
|
||
|
|
ac++, txq++)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_RWNX_FULLMAC
|
||
|
|
struct rwnx_txq *rwnx_txq_sta_get(struct rwnx_sta *sta, u8 tid,
|
||
|
|
struct rwnx_hw *rwnx_hw);
|
||
|
|
struct rwnx_txq *rwnx_txq_vif_get(struct rwnx_vif *vif, u8 type);
|
||
|
|
#endif /* CONFIG_RWNX_FULLMAC */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* rwnx_txq_vif_get_status - return status bits related to the vif
|
||
|
|
*
|
||
|
|
* @rwnx_vif: Pointer to vif structure
|
||
|
|
*/
|
||
|
|
static inline u8 rwnx_txq_vif_get_status(struct rwnx_vif *rwnx_vif)
|
||
|
|
{
|
||
|
|
struct rwnx_txq *txq = rwnx_txq_vif_get(rwnx_vif, 0);
|
||
|
|
return (txq->status & (RWNX_TXQ_STOP_CHAN | RWNX_TXQ_STOP_VIF_PS));
|
||
|
|
}
|
||
|
|
|
||
|
|
void rwnx_txq_vif_init(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif,
|
||
|
|
u8 status);
|
||
|
|
void rwnx_txq_vif_deinit(struct rwnx_hw *rwnx_hw, struct rwnx_vif *vif);
|
||
|
|
void rwnx_txq_sta_init(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta,
|
||
|
|
u8 status);
|
||
|
|
void rwnx_txq_sta_deinit(struct rwnx_hw *rwnx_hw, struct rwnx_sta *rwnx_sta);
|
||
|
|
#ifdef CONFIG_RWNX_FULLMAC
|
||
|
|
void rwnx_txq_unk_vif_init(struct rwnx_vif *rwnx_vif);
|
||
|
|
void rwnx_txq_unk_vif_deinit(struct rwnx_vif *vif);
|
||
|
|
void rwnx_txq_offchan_init(struct rwnx_vif *rwnx_vif);
|
||
|
|
void rwnx_txq_offchan_deinit(struct rwnx_vif *rwnx_vif);
|
||
|
|
void rwnx_txq_tdls_vif_init(struct rwnx_vif *rwnx_vif);
|
||
|
|
void rwnx_txq_tdls_vif_deinit(struct rwnx_vif *vif);
|
||
|
|
void rwnx_txq_tdls_sta_start(struct rwnx_vif *rwnx_vif, u16 reason,
|
||
|
|
struct rwnx_hw *rwnx_hw);
|
||
|
|
void rwnx_txq_tdls_sta_stop(struct rwnx_vif *rwnx_vif, u16 reason,
|
||
|
|
struct rwnx_hw *rwnx_hw);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
void rwnx_txq_add_to_hw_list(struct rwnx_txq *txq);
|
||
|
|
void rwnx_txq_del_from_hw_list(struct rwnx_txq *txq);
|
||
|
|
void rwnx_txq_stop(struct rwnx_txq *txq, u16 reason);
|
||
|
|
void rwnx_txq_start(struct rwnx_txq *txq, u16 reason);
|
||
|
|
void rwnx_txq_vif_start(struct rwnx_vif *vif, u16 reason,
|
||
|
|
struct rwnx_hw *rwnx_hw);
|
||
|
|
void rwnx_txq_vif_stop(struct rwnx_vif *vif, u16 reason,
|
||
|
|
struct rwnx_hw *rwnx_hw);
|
||
|
|
|
||
|
|
#ifdef CONFIG_RWNX_FULLMAC
|
||
|
|
void rwnx_txq_sta_start(struct rwnx_sta *sta, u16 reason,
|
||
|
|
struct rwnx_hw *rwnx_hw);
|
||
|
|
void rwnx_txq_sta_stop(struct rwnx_sta *sta, u16 reason,
|
||
|
|
struct rwnx_hw *rwnx_hw);
|
||
|
|
void rwnx_txq_offchan_start(struct rwnx_hw *rwnx_hw);
|
||
|
|
void rwnx_txq_sta_switch_vif(struct rwnx_sta *sta, struct rwnx_vif *old_vif,
|
||
|
|
struct rwnx_vif *new_vif);
|
||
|
|
|
||
|
|
#endif /* CONFIG_RWNX_FULLMAC */
|
||
|
|
|
||
|
|
int rwnx_txq_queue_skb(struct sk_buff *skb, struct rwnx_txq *txq,
|
||
|
|
struct rwnx_hw *rwnx_hw, bool retry);
|
||
|
|
void rwnx_txq_confirm_any(struct rwnx_hw *rwnx_hw, struct rwnx_txq *txq,
|
||
|
|
struct rwnx_hwq *hwq, struct rwnx_sw_txhdr *sw_txhdr);
|
||
|
|
|
||
|
|
|
||
|
|
void rwnx_hwq_init(struct rwnx_hw *rwnx_hw);
|
||
|
|
void rwnx_hwq_process(struct rwnx_hw *rwnx_hw, struct rwnx_hwq *hwq);
|
||
|
|
void rwnx_hwq_process_all(struct rwnx_hw *rwnx_hw);
|
||
|
|
|
||
|
|
#endif /* _RWNX_TXQ_H_ */
|