rk3588-game
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更新u-boot

This commit is contained in:
liiir1985 2024-06-23 20:20:40 +08:00
parent 7f62dcda9f
commit 2c2dead122
264 changed files with 32398 additions and 2698 deletions

6
u-boot/Kconfig
View File

@ -168,6 +168,12 @@ endmenu # General setup
menu "Boot images"
config IMAGE_GZIP
bool "U-Boot Image with gzip compression"
default n
help
This enables gzip compression on U-Boot Image.
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
default y if FASTBOOT

19
u-boot/Makefile
View File

@ -85,6 +85,13 @@ else
Q = @
endif
ifeq ("$(origin FWVER)", "command line")
PLAT_FW_VERSION := $(FWVER)
endif
ifeq ("$(origin SPL_FWVER)", "command line")
PLAT_SPL_FW_VERSION := $(SPL_FWVER)
endif
# If the user is running make -s (silent mode), suppress echoing of
# commands
@ -1369,6 +1376,12 @@ ifeq ($(CONFIG_SUPPORT_USBPLUG),)
define filechk_version.h
(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
if [ -n "$(PLAT_SPL_FW_VERSION)" ]; then \
echo \#define BUILD_SPL_TAG \"$(PLAT_SPL_FW_VERSION)\"; \
fi; \
if [ -n "$(PLAT_FW_VERSION)" ]; then \
echo \#define BUILD_TAG \"$(PLAT_FW_VERSION)\"; \
fi; \
echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
endef
@ -1376,6 +1389,12 @@ else
define filechk_version.h
(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
echo \#define U_BOOT_VERSION \"USB-PLUG \" PLAIN_VERSION; \
if [ -n "$(PLAT_SPL_FW_VERSION)" ]; then \
echo \#define BUILD_SPL_TAG \"$(PLAT_SPL_FW_VERSION)\"; \
fi; \
if [ -n "$(PLAT_FW_VERSION)" ]; then \
echo \#define BUILD_TAG \"$(PLAT_FW_VERSION)\"; \
fi; \
echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
endef

2
u-boot/arch/arm/cpu/armv7/arch_timer.c
View File

@ -41,5 +41,5 @@ ulong timer_get_boot_us(void)
ulong get_tbclk(void)
{
return gd->arch.timer_rate_hz;
return gd->arch.timer_rate_hz ? : CONFIG_SYS_HZ_CLOCK;
}

8
u-boot/arch/arm/dts/rk3308.dtsi
View File

@ -300,7 +300,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
status = "disabled";
};
@ -311,7 +311,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
status = "disabled";
};
@ -322,7 +322,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
status = "disabled";
};
@ -333,7 +333,7 @@
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
status = "disabled";
};

5
u-boot/arch/arm/dts/rk3528-u-boot.dtsi
View File

@ -37,6 +37,11 @@
status = "okay";
};
&combphy_pu {
u-boot,dm-pre-reloc;
status = "okay";
};
&cru {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;

2
u-boot/arch/arm/dts/rk3568-u-boot.dtsi
View File

@ -387,7 +387,7 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
status = "okay";
};

18
u-boot/arch/arm/dts/rk3588-u-boot.dtsi
View File

@ -193,6 +193,24 @@
status = "okay";
};
&usb_grf{
u-boot,dm-pre-reloc;
};
&usbdpphy0_grf{
u-boot,dm-pre-reloc;
};
&usbdp_phy0{
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdp_phy0_u3{
u-boot,dm-pre-reloc;
status = "okay";
};
/* Support SPL-PINCTRL:
* 1. ioc
* 2. pinctrl(sdmmc)

1
u-boot/arch/arm/dts/rk3588.dtsi
View File

@ -467,6 +467,7 @@
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
rockchip,u2phy-grf = <&usb2phy1_grf>;
rockchip,usb-grf = <&usb_grf>;
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
rockchip,vo-grf = <&vo0_grf>;

1
u-boot/arch/arm/dts/rk3588s.dtsi
View File

@ -2260,6 +2260,7 @@
usbdp_phy0: phy@fed80000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed80000 0x0 0x10000>;
rockchip,u2phy-grf = <&usb2phy0_grf>;
rockchip,usb-grf = <&usb_grf>;
rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
rockchip,vo-grf = <&vo0_grf>;

4
u-boot/arch/arm/dts/rv1106-evb.dts
View File

@ -30,3 +30,7 @@
};
};
&hw_decompress {
u-boot,dm-spl;
status = "okay";
};

9
u-boot/arch/arm/dts/rv1106-evb2.dts
View File

@ -22,7 +22,7 @@
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
keyup-threshold-microvolt = <893000>;
u-boot,dm-spl;
status = "okay";
@ -30,6 +30,13 @@
u-boot,dm-spl;
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <339589>;
};
volumedown-key {
u-boot,dm-spl;
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <17578>;
};
};

5
u-boot/arch/arm/dts/rv1106.dtsi
View File

@ -861,8 +861,11 @@
wdt: watchdog@ff5a0000 {
compatible = "rockchip,rv1106-wdt", "snps,dw-wdt";
reg = <0xff5a0000 0x100>;
clocks = <&cru PCLK_WDT_NS>;
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
clock-names = "tclk", "pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_P_WDT_NS>;
reset-names = "reset";
status = "disabled";
};

4
u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
View File

@ -124,10 +124,10 @@ struct pll_rate_table {
#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
#define RK3528_DIV_PCLK_DBG_MASK 0x1f
#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT)
#define RK3528_DIV_PCLK_DBG_SHIFT 1
#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT)
enum {
/* CRU_CLKSEL_CON00 */

26
u-boot/arch/arm/include/asm/arch-rockchip/rk_atags.h
View File

@ -21,6 +21,7 @@
#define ATAG_SOC_INFO 0x54410057
#define ATAG_BOOT1_PARAM 0x54410058
#define ATAG_PSTORE 0x54410059
#define ATAG_FWVER 0x5441005a
#define ATAG_MAX 0x544100ff
/* Tag size and offset */
@ -75,6 +76,17 @@
/* tag_ddr_mem.flags */
#define DDR_MEM_FLG_EXT_TOP 1
/* tag_fwver.ver[fwid][] */
#define FWVER_LEN 36
enum fwid {
FW_DDR,
FW_SPL,
FW_ATF,
FW_TEE,
FW_MAX,
};
struct tag_serial {
u32 version;
u32 enable;
@ -183,6 +195,12 @@ struct tag_pstore {
u32 hash;
} __packed;
struct tag_fwver {
u32 version;
char ver[8][FWVER_LEN];
u32 hash;
} __packed;
struct tag_core {
u32 flags;
u32 pagesize;
@ -209,6 +227,7 @@ struct tag {
struct tag_soc_info soc;
struct tag_boot1p boot1p;
struct tag_pstore pstore;
struct tag_fwver fwver;
} u;
} __aligned(4);
@ -266,6 +285,13 @@ int atags_overflow(struct tag *t);
*/
int atags_bad_magic(u32 magic);
/*
* atags_set_shared_fwver - set fwver tag.
*
* return: 0 on success, otherwise failed.
*/
int atags_set_shared_fwver(u32 fwid, char *ver);
#ifdef CONFIG_SPL_BUILD
/*
* get_bootdev_by_brom_bootsource

1
u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h
View File

@ -95,6 +95,7 @@ typedef enum {
SHARE_PAGE_TYPE_DDR_ADDRMAP,
SHARE_PAGE_TYPE_LAST_LOG,
SHARE_PAGE_TYPE_HDCP,
SHARE_PAGE_TYPE_SLEEP,
SHARE_PAGE_TYPE_MAX,
} share_page_type_t;

17
u-boot/arch/arm/lib/interrupts_64.c
View File

@ -10,6 +10,9 @@
#include <efi_loader.h>
#include <iomem.h>
#include <stacktrace.h>
#ifdef CONFIG_ROCKCHIP_MINIDUMP
#include <rk_mini_dump.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -181,6 +184,13 @@ void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
void do_sync(struct pt_regs *pt_regs, unsigned int esr)
{
efi_restore_gd();
#ifdef CONFIG_ROCKCHIP_MINIDUMP
if (md_no_fault_handler(pt_regs, esr)) {
/* Return to next instruction */
pt_regs->elr += 4;
return;
}
#endif
printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
@ -219,6 +229,13 @@ void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
{
efi_restore_gd();
#ifdef CONFIG_ROCKCHIP_MINIDUMP
if (md_no_fault_handler(pt_regs, esr)) {
/* Return to next instruction */
pt_regs->elr += 4;
return;
}
#endif
printf("\"Error\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");

31
u-boot/arch/arm/mach-rockchip/Kconfig
View File

@ -487,7 +487,7 @@ config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_TEXT_BASE
default 0xfdcc1000
default 0xff001000
config TPL_MAX_SIZE
default 61440
@ -846,7 +846,7 @@ config ROCKCHIP_HWID_DTB
config ROCKCHIP_VENDOR_PARTITION
bool "Rockchip vendor storage partition support"
depends on RKIMG_BOOTLOADER
depends on (RKIMG_BOOTLOADER || SUPPORT_USBPLUG)
help
This enable support to read/write vendor configuration data from/to
this partition.
@ -1101,6 +1101,33 @@ config PERSISTENT_RAM_SIZE
This select linux pstore buffer size for U-Boot, the value must be
set if PERSISTENT_RAM_ADDR != 0.
config ROCKCHIP_MINIDUMP
bool "Minidump Save Linux Debug Data To Ram Elf"
default n
help
This enable saving linux debug data to a reserved memory as a elf file.
config ROCKCHIP_MINIDUMP_SMEM_BASE
hex "The base of share memory between Uboot and Linux"
default 0x1f0000
depends on ROCKCHIP_MINIDUMP
help
This select the base address of share memory, which is behind PSTORE.
config ROCKCHIP_MINIDUMP_MAX_ELF_SIZE
hex "The max size of minidump elf"
default 0x2000000
depends on ROCKCHIP_MINIDUMP
help
This is used to judge the elf program size and section size.
config ROCKCHIP_MINIDUMP_MAX_ENTRIES
hex "The max entries of minidump region"
default 0x200
depends on ROCKCHIP_MINIDUMP
help
This sets the max entries of minidump region.
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3066/Kconfig"

2
u-boot/arch/arm/mach-rockchip/Makefile
View File

@ -92,3 +92,5 @@ obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
obj-$(CONFIG_ROCKCHIP_PRELOADER_ATAGS) += rk_atags.o
obj-$(CONFIG_SET_DFU_ALT_INFO) += dfu_alt_info.o
obj-$(CONFIG_PSTORE) += pstore.o
obj-$(CONFIG_ROCKCHIP_MINIDUMP) += rk_mini_dump.o

263
u-boot/arch/arm/mach-rockchip/board.c
View File

@ -5,6 +5,8 @@
*/
#include <common.h>
#include <version.h>
#include <abuf.h>
#include <amp.h>
#include <android_ab.h>
#include <android_bootloader.h>
@ -26,6 +28,7 @@
#include <of_live.h>
#include <mtd_blk.h>
#include <ram.h>
#include <rng.h>
#include <rockchip_debugger.h>
#include <syscon.h>
#include <sysmem.h>
@ -53,8 +56,9 @@
#ifdef CONFIG_ROCKCHIP_EINK_DISPLAY
#include <rk_eink.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ROCKCHIP_MINIDUMP
#include <rk_mini_dump.h>
#endif
#ifdef CONFIG_ARM64
static ulong orig_images_ep;
@ -98,7 +102,6 @@ __weak int rk_board_init(void)
*/
#define VENDOR_SN_MAX 513
#define CPUID_LEN 0x10
#define CPUID_OFF 0x07
#define MAX_ETHERNET 0x2
@ -175,10 +178,13 @@ static int rockchip_set_serialno(void)
for (i = 0; i < j; i++) {
if ((serialno_str[i] >= 'a' && serialno_str[i] <= 'z') ||
(serialno_str[i] >= 'A' && serialno_str[i] <= 'Z') ||
(serialno_str[i] >= '0' && serialno_str[i] <= '9'))
(serialno_str[i] >= '0' && serialno_str[i] <= '9')) {
continue;
else
} else {
if (i > 0)
serialno_str[i] = 0x0;
break;
}
}
/* valid character count > 0 */
@ -208,7 +214,7 @@ static int rockchip_set_serialno(void)
}
/* read the cpu_id range from the efuses */
ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
ret = misc_read(dev, CFG_CPUID_OFFSET, &cpuid, sizeof(cpuid));
if (ret) {
printf("%s: read cpuid from efuse/otp failed, ret=%d\n",
__func__, ret);
@ -461,6 +467,11 @@ int board_late_init(void)
#ifdef CONFIG_DM_CHARGE_DISPLAY
charge_display();
#endif
#ifdef CONFIG_ROCKCHIP_MINIDUMP
rk_minidump_init();
#endif
#ifdef CONFIG_DRM_ROCKCHIP
if (rockchip_get_boot_mode() != BOOT_MODE_QUIESCENT)
rockchip_show_logo();
@ -544,7 +555,6 @@ int board_init(void)
if (ab_decrease_tries())
printf("Decrease ab tries count fail!\n");
#endif
return rk_board_init();
}
@ -894,7 +904,7 @@ int bootm_board_start(void)
* we switch to uart debug function in order to print it after loading
* images.
*/
#if defined(CONFIG_CONSOLE_RECORD)
#if 0
if (!strcmp("mmc", env_get("devtype")) &&
!strcmp("1", env_get("devnum"))) {
printf("IOMUX: sdmmc => uart debug");
@ -1115,47 +1125,142 @@ void board_quiesce_devices(void *images)
#endif
}
char *board_fdt_chosen_bootargs(void *fdt)
/*
* Use hardware rng to seed Linux random
*
* 'Android_14 + GKI' requires this information.
*/
int board_rng_seed(struct abuf *buf)
{
/* bootargs_ext is used when dtbo is applied. */
const char *arr_bootargs[] = { "bootargs", "bootargs_ext" };
const char *bootargs;
int nodeoffset;
int i, dump;
char *msg = "kernel";
/* debug */
hotkey_run(HK_INITCALL);
dump = is_hotkey(HK_CMDLINE);
if (dump)
printf("## bootargs(u-boot): %s\n\n", env_get("bootargs"));
/* find or create "/chosen" node. */
nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
if (nodeoffset < 0)
return NULL;
for (i = 0; i < ARRAY_SIZE(arr_bootargs); i++) {
bootargs = fdt_getprop(fdt, nodeoffset, arr_bootargs[i], NULL);
if (!bootargs)
continue;
if (dump)
printf("## bootargs(%s-%s): %s\n\n",
msg, arr_bootargs[i], bootargs);
/*
* Append kernel bootargs
* If use AB system, delete default "root=" which route
* to rootfs. Then the ab bootctl will choose the
* high priority system to boot and add its UUID
* to cmdline. The format is "roo=PARTUUID=xxxx...".
*/
#ifdef CONFIG_ANDROID_AB
env_update_filter("bootargs", bootargs, "root=");
#else
env_update("bootargs", bootargs);
#ifdef CONFIG_DM_RNG
struct udevice *dev;
#endif
size_t len = 32;
u8 *data;
int i;
data = malloc(len);
if (!data) {
printf("Out of memory\n");
return -ENOMEM;
}
#ifdef CONFIG_DM_RNG
if (uclass_get_device(UCLASS_RNG, 0, &dev) || dm_rng_read(dev, data, len))
#endif
{
printf("board seed: Pseudo\n");
for (i = 0; i < len; i++)
data[i] = (u8)rand();
}
abuf_init_set(buf, data, len);
return 0;
}
/*
* Pass fwver when any available.
*/
static void bootargs_add_fwver(bool verbose)
{
#ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
struct tag *t;
char *list1 = NULL;
char *list2 = NULL;
char *fwver = NULL;
char *p = PLAIN_VERSION;
int i, end;
t = atags_get_tag(ATAG_FWVER);
if (t) {
list1 = calloc(1, sizeof(struct tag_fwver));
if (!list1)
return;
for (i = 0; i < FW_MAX; i++) {
if (t->u.fwver.ver[i][0] != '\0') {
strcat(list1, t->u.fwver.ver[i]);
strcat(list1, ",");
}
}
}
list2 = calloc(1, FWVER_LEN);
if (!list2)
goto out;
strcat(list2, "uboot-");
/* optional */
#ifdef BUILD_TAG
strcat(list2, BUILD_TAG);
strcat(list2, "-");
#endif
/* optional */
if (strcmp(PLAIN_VERSION, "2017.09")) {
strncat(list2, p + strlen("2017.09-g"), 10);
strcat(list2, "-");
}
strcat(list2, U_BOOT_DMI_DATE);
/* merge ! */
if (list1 || list2) {
fwver = calloc(1, sizeof(struct tag_fwver));
if (!fwver)
goto out;
strcat(fwver, "androidboot.fwver=");
if (list1)
strcat(fwver, list1);
if (list2) {
strcat(fwver, list2);
} else {
end = strlen(fwver) - 1;
fwver[end] = '\0'; /* omit last ',' */
}
if (verbose)
printf("## fwver: %s\n\n", fwver);
env_update("bootargs", fwver);
env_set("fwver", fwver + strlen("androidboot."));
}
out:
if (list1)
free(list1);
if (list2)
free(list2);
if (fwver)
free(fwver);
#endif
}
static void bootargs_add_android(bool verbose)
{
#ifdef CONFIG_ANDROID_AB
ab_update_root_partition();
#endif
/* Android header v4+ need this handle */
#ifdef CONFIG_ANDROID_BOOT_IMAGE
struct andr_img_hdr *hdr;
char *fwver;
hdr = (void *)env_get_ulong("android_addr_r", 16, 0);
if (hdr && !android_image_check_header(hdr) && hdr->header_version >= 4) {
if (env_update_extract_subset("bootargs", "andr_bootargs", "androidboot."))
printf("extract androidboot.xxx error\n");
if (verbose)
printf("## bootargs(android): %s\n\n", env_get("andr_bootargs"));
/* for kernel cmdline can be read */
fwver = env_get("fwver");
if (fwver) {
env_update("bootargs", fwver);
env_set("fwver", NULL);
}
}
#endif
}
static void bootargs_add_partition(bool verbose)
{
#if defined(CONFIG_ENVF) || defined(CONFIG_ENV_PARTITION)
char *part_type[] = { "mtdparts", "blkdevparts" };
char *part_list;
@ -1177,14 +1282,14 @@ char *board_fdt_chosen_bootargs(void *fdt)
part_list = env;
}
env_update("bootargs", part_list);
if (dump)
if (verbose)
printf("## parts: %s\n\n", part_list);
}
env = env_get("sys_bootargs");
if (env) {
env_update("bootargs", env);
if (dump)
if (verbose)
printf("## sys_bootargs: %s\n\n", env);
}
#endif
@ -1199,10 +1304,58 @@ char *board_fdt_chosen_bootargs(void *fdt)
}
}
#endif
}
static void bootargs_add_dtb_dtbo(void *fdt, bool verbose)
{
/* bootargs_ext is used when dtbo is applied. */
const char *arr_bootargs[] = { "bootargs", "bootargs_ext" };
const char *bootargs;
char *msg = "kernel";
int i, noffset;
/* find or create "/chosen" node. */
noffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
if (noffset < 0)
return;
for (i = 0; i < ARRAY_SIZE(arr_bootargs); i++) {
bootargs = fdt_getprop(fdt, noffset, arr_bootargs[i], NULL);
if (!bootargs)
continue;
if (verbose)
printf("## bootargs(%s-%s): %s\n\n",
msg, arr_bootargs[i], bootargs);
/*
* Append kernel bootargs
* If use AB system, delete default "root=" which route
* to rootfs. Then the ab bootctl will choose the
* high priority system to boot and add its UUID
* to cmdline. The format is "roo=PARTUUID=xxxx...".
*/
#ifdef CONFIG_ANDROID_AB
ab_update_root_partition();
env_update_filter("bootargs", bootargs, "root=");
#else
env_update("bootargs", bootargs);
#endif
}
}
char *board_fdt_chosen_bootargs(void *fdt)
{
int verbose = is_hotkey(HK_CMDLINE);
const char *bootargs;
/* debug */
hotkey_run(HK_INITCALL);
if (verbose)
printf("## bootargs(u-boot): %s\n\n", env_get("bootargs"));
bootargs_add_dtb_dtbo(fdt, verbose);
bootargs_add_partition(verbose);
bootargs_add_fwver(verbose);
bootargs_add_android(verbose);
/*
* Initrd fixup: remove unused "initrd=0x...,0x...",
* this for compatible with legacy parameter.txt
@ -1225,20 +1378,8 @@ char *board_fdt_chosen_bootargs(void *fdt)
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
env_delete("bootargs", "earlycon=", 0);
/* Android header v4+ need this handle */
#ifdef CONFIG_ANDROID_BOOT_IMAGE
struct andr_img_hdr *hdr;
hdr = (void *)env_get_ulong("android_addr_r", 16, 0);
if (hdr && !android_image_check_header(hdr) && hdr->header_version >= 4) {
if (env_update_extract_subset("bootargs", "andr_bootargs", "androidboot."))
printf("extract androidboot.xxx error\n");
if (dump)
printf("## bootargs(android): %s\n\n", env_get("andr_bootargs"));
}
#endif
bootargs = env_get("bootargs");
if (dump)
if (verbose)
printf("## bootargs(merged): %s\n\n", bootargs);
return (char *)bootargs;

4
u-boot/arch/arm/mach-rockchip/fit_nodes.sh
View File

@ -347,6 +347,10 @@ if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
else
ALGO_NAME=" algo = \"sha256,rsa2048\";"
fi
if [ -z "${LOADABLE_ATF}" ]; then
LOADABLE_UBOOT="\"uboot\""
fi
echo " };
configurations {

2
u-boot/arch/arm/mach-rockchip/memblk.c
View File

@ -41,7 +41,7 @@ const static struct memblk_attr plat_mem_attr[MEM_MAX] = {
MEM_DEFINE(ANDROID, F_HOFC | F_OFC | F_KMEM_CAN_OVERLAP),
MEM_DEFINE(FDT, F_OFC),
MEM_DEFINE(FDT_DTBO, F_OFC),
MEM_DEFINE_1(SHM, F_NONE, "ramoops"),
MEM_DEFINE_2(SHM, F_NONE, "ramoops", "minidump"),
MEM_DEFINE_2(RAMDISK, F_OFC, "boot", "recovery"),
MEM_DEFINE(UNCOMP_KERNEL,F_IGNORE_INVISIBLE),
MEM_DEFINE(FIT_USER, F_OFC | F_KMEM_CAN_OVERLAP),

7
u-boot/arch/arm/mach-rockchip/pstore.c
View File

@ -138,15 +138,18 @@ void putc_to_ram(const char c)
if (!rb || pstore_size == 0)
return;
if (rb->start >= pstore_size)
rb->start = 0;
dst = rb->data + rb->start;
*dst = c;
if (rb->size < pstore_size)
rb->size++;
else
rb->size = pstore_size;
rb->start++;
if (rb->start >= pstore_size)
rb->start = 0;
}
void puts_to_ram(const char *str)

16
u-boot/arch/arm/mach-rockchip/rk3308/rk3308.c
View File

@ -187,6 +187,10 @@ int rk_board_init(void)
#define QOS_PRIORITY_P1_P0(p1, p0) ((((p1) & 0x3) << 8) |\
(((p0) & 0x3) << 0))
#define CRU_CLKGATE_CON10 0x0328
#define CRU_CLKGATE_CON11 0x032c
#define CRU_CLKGATE_CON12 0x0330
enum {
IOVSEL4_SHIFT = 4,
IOVSEL4_MASK = BIT(4),
@ -202,6 +206,18 @@ int arch_cpu_init(void)
/* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
rk_clrreg(&sgrf->con_secure0, 0x2b83);
#else /* uboot */
/*
* Gate I2Sx_MCLK default
*
* It's safe to gate mclk default to avoid high freq glitch
* which may make devices work unexpected. And then enabled by
* kernel stage or any state where user use it.
*/
writel(0x80008000, CRU_BASE + CRU_CLKGATE_CON10);
writel(0x88888888, CRU_BASE + CRU_CLKGATE_CON11);
writel(0x88888888, CRU_BASE + CRU_CLKGATE_CON12);
#endif
#else /* defined(CONFIG_TPL_BUILD) */
static struct rk3308_cru * const cru = (void *)CRU_BASE;

24
u-boot/arch/arm/mach-rockchip/rk3562/rk3562.c
View File

@ -96,6 +96,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define VICAP_PRIORITY_REG 0xfee70108
#define VOP_PRIORITY_REG 0xfee80008
#define PCIE_SHAPING_REG 0xfeea0088
#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
#ifdef CONFIG_ARM64
@ -506,16 +508,17 @@ int fit_standalone_release(char *id, uintptr_t entry_point)
/* open bus m0 sclk / bus m0 hclk / bus m0 dclk */
writel(0x00070000, TOP_CRU_BASE + TOP_CRU_CM0_GATEMASK);
/* mcu_cache_peripheral_addr */
writel(0xa0000000, SYS_GRF_BASE + SYS_GRF_SOC_CON5);
/*
* mcu_cache_peripheral_addr
* The uncache area ranges from 0x7c00000 to 0xffb400000
* and contains rpmsg shared memory
*/
writel(0x07c00000, SYS_GRF_BASE + SYS_GRF_SOC_CON5);
writel(0xffb40000, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
0xffff0000 | (entry_point >> 16));
/* 0x07c00000 is mapped to 0xa0000000 and used as shared memory for rpmsg */
sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR, 0xffff07c0);
/* release dcache / icache / bus m0 jtag / bus m0 */
writel(0x03280000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON23);
@ -532,7 +535,7 @@ static void qos_priority_init(void)
u32 delay;
u32 i;
/* power up vo,vi,gpu */
/* power up vo,vi */
rk_clrreg(PMU_BASE_ADDR + PMU2_PWR_GATE_SFTCON0,
PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA);
delay = 1000;
@ -605,6 +608,8 @@ static void qos_priority_init(void)
writel(QOS_PRIORITY_LEVEL(2, 2), DCF_PRIORITY_REG);
writel(QOS_PRIORITY_LEVEL(2, 2), DMA2DDR_PRIORITY_REG);
writel(QOS_PRIORITY_LEVEL(2, 2), PCIE_PRIORITY_REG);
writel(0x5, PCIE_SHAPING_REG);
}
int arch_cpu_init(void)
@ -631,6 +636,13 @@ int arch_cpu_init(void)
/* Assert reset the pipe phy to save power and de-assert when in use */
writel(0x00030001, PIPEPHY_GRF_BASE + PIPEPHY_PIPE_CON5);
#if defined(CONFIG_SUPPORT_USBPLUG)
/* Set emmc iomux */
writel(0xffff1111, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
writel(0xffff1111, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
writel(0xffff1111, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
#endif
#if defined(CONFIG_ROCKCHIP_SFC)
/* Set the fspi to access ddr memory */
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);

210
u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <misc.h>
#include <mmc.h>
#include <spl.h>
@ -58,10 +59,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define BUS_IOC_BASE 0xfd5f8000
#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
#define BUS_IOC_GPIO2A_IOMUX_SEL_H 0x44
#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
#define BUS_IOC_GPIO2B_IOMUX_SEL_H 0x4c
#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
#define BUS_IOC_GPIO3A_IOMUX_SEL_H 0x64
#define BUS_IOC_GPIO3C_IOMUX_SEL_H 0x74
#define VCCIO3_5_IOC_BASE 0xfd5fa000
#define IOC_VCCIO3_5_GPIO2A_DS_H 0x44
@ -110,7 +115,13 @@ static struct mm_region rk3588_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
}, {
.virt = 0x100000000UL,
.phys = 0x100000000UL,
.size = 0x700000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x900000000,
.phys = 0x900000000,
.size = 0x150000000,
@ -844,6 +855,57 @@ void spl_board_storages_fixup(struct spl_image_loader *loader)
}
#endif
void board_set_iomux(enum if_type if_type, int devnum, int routing)
{
switch (if_type) {
case IF_TYPE_MMC:
/*
* set the emmc io drive strength:
* data and cmd: 50ohm
* clock: 25ohm
*/
writel(0x00770052, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
/* set emmc iomux */
writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
break;
case IF_TYPE_MTD:
if (routing == 0) {
writel(0x000f0002, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
writel(0xffff2222, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
writel(0x00f00020, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
/* Set the fspi m0 io ds level to 55ohm */
writel(0x00070002, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
writel(0x07000200, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
} else if (routing == 1) {
writel(0xff003300, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_H);
writel(0xf0ff3033, BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_L);
writel(0x000f0003, BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_H);
/* Set the fspi m1 io ds level to 55ohm */
writel(0x33002200, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2A_DS_H);
writel(0x30332022, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_L);
writel(0x00030002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_H);
} else if (routing == 2) {
writel(0xffff5555, BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_L);
writel(0x00f00050, BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_H);
writel(0x00ff0022, BUS_IOC_BASE + BUS_IOC_GPIO3C_IOMUX_SEL_H);
/* Set the fspi m2 io ds level to 55ohm */
writel(0x77772222, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_L);
writel(0x00700020, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_H);
writel(0x00070002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3C_DS_H);
}
break;
default:
break;
}
}
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
@ -939,6 +1001,41 @@ int arch_cpu_init(void)
writel(0x00030003, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON04);
spl_board_sd_iomux_save();
#elif defined(CONFIG_SUPPORT_USBPLUG)
int secure_reg;
/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
secure_reg &= 0xffff0000;
writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
secure_reg &= 0xffff;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
secure_reg &= 0xffff0000;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
#else /* U-Boot */
/* uboot: config iomux */
#ifdef CONFIG_ROCKCHIP_EMMC_IOMUX
@ -966,12 +1063,24 @@ int arch_cpu_init(void)
#define BAD_CPU(mask, n) ((mask) & (1 << (n)))
#define BAD_RKVENC(mask, n) ((mask) & (1 << (n)))
#define BAD_RKVDEC(mask, n) ((mask) & (1 << (n)))
static void fdt_rm_path(void *blob, const char *path)
{
fdt_del_node(blob, fdt_path_offset(blob, path));
}
static void fdt_rename_path(void *blob, const char *path, const char *name)
{
int noffset;
noffset = fdt_path_offset(blob, path);
if (noffset < 0)
return;
fdt_set_name(blob, noffset, name);
}
static void fdt_rm_cooling_map(const void *blob, u8 cpu_mask)
{
int map1, map2;
@ -1104,7 +1213,7 @@ static void fdt_rm_cpu(const void *blob, u8 cpu_mask)
}
}
static void fdt_rm_cpus(const void *blob, u8 cpu_mask)
static void rk3582_fdt_rm_cpus(const void *blob, u8 cpu_mask)
{
/*
* policy:
@ -1127,7 +1236,7 @@ static void fdt_rm_cpus(const void *blob, u8 cpu_mask)
fdt_rm_cpu(blob, cpu_mask);
}
static void fdt_rm_gpu(void *blob)
static void rk3582_fdt_rm_gpu(void *blob)
{
/*
* policy:
@ -1139,7 +1248,7 @@ static void fdt_rm_gpu(void *blob)
debug("rm: gpu\n");
}
static void fdt_rm_rkvdec01(void *blob)
static void rk3582_fdt_rm_rkvdec01(void *blob)
{
/*
* policy:
@ -1153,13 +1262,15 @@ static void fdt_rm_rkvdec01(void *blob)
debug("rm: rkvdec0, rkvdec1\n");
}
static void fdt_rm_rkvenc01(void *blob, u8 mask)
static void rk3582_fdt_rm_rkvenc01(void *blob, u8 mask)
{
/*
* policy:
*
* 1. remove bad.
* 2. if both of rkvenc0 and rkvenc1 are normal, remove rkvenc1 by default.
* 3. disable '*-ccu' node
* 4. rename '*-core@' node
*/
if (!BAD_RKVENC(mask, 0) && !BAD_RKVENC(mask, 1)) {
/* rkvenc1 */
@ -1179,6 +1290,50 @@ static void fdt_rm_rkvenc01(void *blob, u8 mask)
debug("rm: rkvenv1\n");
}
}
do_fixup_by_path((void *)blob, "/rkvenc-ccu",
"status", "disabled", sizeof("disabled"), 0);
/* rename node name if the node exist, actually only one exist */
fdt_rename_path(blob, "/rkvenc-core@fdbd0000", "rkvenc@fdbd0000");
fdt_rename_path(blob, "/rkvenc-core@fdbe0000", "rkvenc@fdbe0000");
}
static void rk3583_fdt_rm_rkvdec01(void *blob, u8 mask)
{
/*
* policy:
*
* 1. remove bad.
* 2. if both of rkvdec0 and rkvdec1 are normal, remove rkvdec1 by default.
* 3. disable '*-ccu' node
* 4. rename '*-core@' node
*/
if (!BAD_RKVDEC(mask, 0) && !BAD_RKVDEC(mask, 1)) {
/* rkvdec1 */
fdt_rm_path(blob, "/rkvdec-core@fdc48000");
fdt_rm_path(blob, "/iommu@fdc48700");
debug("rm: rkvdec1\n");
} else {
if (BAD_RKVDEC(mask, 0)) {
fdt_rm_path(blob, "/rkvdec-core@fdc38000");
fdt_rm_path(blob, "/iommu@fdc38700");
debug("rm: rkvdec0\n");
}
if (BAD_RKVDEC(mask, 1)) {
fdt_rm_path(blob, "/rkvdec-core@fdc48000");
fdt_rm_path(blob, "/iommu@fdc48700");
debug("rm: rkvdec1\n");
}
}
do_fixup_by_path((void *)blob, "/rkvdec-ccu@fdc30000",
"status", "disabled", sizeof("disabled"), 0);
/* rename node name if the node exist, actually only one exist */
fdt_rename_path(blob, "/rkvdec-core@fdc38000", "rkvdec@fdc38000");
fdt_rename_path(blob, "/rkvdec-core@fdc48000", "rkvdec@fdc48000");
}
#define CHIP_ID_OFF 2
@ -1190,6 +1345,7 @@ static int fdt_fixup_modules(void *blob)
u8 ip_state[3];
u8 chip_id[2];
u8 rkvenc_mask;
u8 rkvdec_mask;
u8 cpu_mask;
int ret;
@ -1208,8 +1364,9 @@ static int fdt_fixup_modules(void *blob)
debug("# chip: rk%02x%02x\n", chip_id[0], chip_id[1]);
/* only rk3582 goes further */
if (!(chip_id[0] == 0x35 && chip_id[1] == 0x82))
/* only rk3582/rk3583 goes further */
if (!(chip_id[0] == 0x35 && chip_id[1] == 0x82) &&
!(chip_id[0] == 0x35 && chip_id[1] == 0x83))
return 0;
ret = misc_read(dev, IP_STATE_OFF, &ip_state, sizeof(ip_state));
@ -1222,33 +1379,42 @@ static int fdt_fixup_modules(void *blob)
cpu_mask = ip_state[0];
/* ip_state[2]: bit0,2 */
rkvenc_mask = (ip_state[2] & 0x1) | ((ip_state[2] & 0x4) >> 1);
/* ip_state[1]: bit6,7 */
rkvdec_mask = (ip_state[1] & 0xc0) >> 6;
#if 0
/* ip_state[1]: bit1~4 */
gpu_mask = (ip_state[1] & 0x1e) >> 1;
/* ip_state[1]: bit6,7 */
rkvdec_mask = (ip_state[1] & 0xc0) >> 6;
#endif
debug("hwmask: 0x%02x, 0x%02x, 0x%02x\n", ip_state[0], ip_state[1], ip_state[2]);
debug("swmask: 0x%02x, 0x%02x\n", cpu_mask, rkvenc_mask);
debug("hw-mask: 0x%02x, 0x%02x, 0x%02x\n", ip_state[0], ip_state[1], ip_state[2]);
debug("sw-mask: 0x%02x, 0x%02x, 0x%02x\n", cpu_mask, rkvenc_mask, rkvdec_mask);
/*
* RK3582 Policy: gpu/rkvdec are removed by default, the same for other
* IP under some condition.
*
* So don't use pattern like "if (rkvenc_mask) then fdt_rm_rkvenc01()",
* just go through all of them as this chip is rk3582.
*
* FIXUP WARNING!
*
* The node delete changes the fdt structure, a node offset you already
* got before maybe not right by now. Make sure always reading the node
* offset exactly before you are going to use.
*/
fdt_rm_gpu(blob);
fdt_rm_rkvdec01(blob);
fdt_rm_rkvenc01(blob, rkvenc_mask);
fdt_rm_cpus(blob, cpu_mask);
if (chip_id[0] == 0x35 && chip_id[1] == 0x82) {
/*
* RK3582 Policy: gpu/rkvdec are removed by default, the same for other
* IP under some condition.
*
* So don't use pattern like "if (rkvenc_mask) then rk3582_fdt_rm_rkvenc01()",
* just go through all of them as this chip is rk3582.
*/
rk3582_fdt_rm_gpu(blob);
rk3582_fdt_rm_rkvdec01(blob);
rk3582_fdt_rm_rkvenc01(blob, rkvenc_mask);
rk3582_fdt_rm_cpus(blob, cpu_mask);
} else if (chip_id[0] == 0x35 && chip_id[1] == 0x83) {
/*
* RK3583 Policy: some rules are the same as rk3582.
*/
rk3583_fdt_rm_rkvdec01(blob, rkvdec_mask);
rk3582_fdt_rm_rkvenc01(blob, rkvenc_mask);
rk3582_fdt_rm_cpus(blob, cpu_mask);
}
return 0;
}

46
u-boot/arch/arm/mach-rockchip/rk_atags.c
View File

@ -179,8 +179,9 @@ int atags_is_available(void)
int atags_set_tag(u32 magic, void *tagdata)
{
u32 length, size = 0, hash;
struct tag *t = (struct tag *)ATAGS_PHYS_BASE;
u32 length, size = 0, hash;
int append = 1; /* 0: override */
#if !defined(CONFIG_TPL_BUILD) && !defined(CONFIG_FPGA_ROCKCHIP)
if (!atags_is_available())
@ -216,8 +217,10 @@ int atags_set_tag(u32 magic, void *tagdata)
return -EINVAL;
/* This is an old tag, override it */
if (t->hdr.magic == magic)
if (t->hdr.magic == magic) {
append = 0;
break;
}
if (t->hdr.magic == ATAG_NONE)
break;
@ -256,6 +259,9 @@ int atags_set_tag(u32 magic, void *tagdata)
case ATAG_PSTORE:
size = tag_size(tag_pstore);
break;
case ATAG_FWVER:
size = tag_size(tag_fwver);
break;
};
if (!size)
@ -264,7 +270,7 @@ int atags_set_tag(u32 magic, void *tagdata)
if (atags_size_overflow(t, size))
return -ENOMEM;
/* It's okay to setup a new tag */
/* It's okay to setup a new tag or override tag */
t->hdr.magic = magic;
t->hdr.size = size;
length = (t->hdr.size << 2) - sizeof(struct tag_header) - HASH_LEN;
@ -272,17 +278,41 @@ int atags_set_tag(u32 magic, void *tagdata)
hash = js_hash(t, (size << 2) - HASH_LEN);
memcpy((char *)&t->u + length, &hash, HASH_LEN);
/* Next tag */
t = tag_next(t);
if (append) {
/* Next tag */
t = tag_next(t);
/* Setup done */
t->hdr.magic = ATAG_NONE;
t->hdr.size = 0;
/* Setup done */
t->hdr.magic = ATAG_NONE;
t->hdr.size = 0;
}
return 0;
}
#ifndef CONFIG_TPL_BUILD
int atags_set_shared_fwver(u32 fwid, char *ver)
{
struct tag_fwver fw = {}, *pfw;
struct tag *t;
if (!ver || (strlen(ver) >= FWVER_LEN) || fwid >= FW_MAX)
return -EINVAL;
t = atags_get_tag(ATAG_FWVER);
if (!t) {
pfw = &fw;
pfw->version = 0;
} else {
pfw = &t->u.fwver;
}
strcpy(pfw->ver[fwid], ver);
atags_set_tag(ATAG_FWVER, pfw);
return 0;
}
struct tag *atags_get_tag(u32 magic)
{
u32 *hash, calc_hash, size;

535
u-boot/arch/arm/mach-rockchip/rk_mini_dump.c Normal file
View File

@ -0,0 +1,535 @@
/*
* (C) Copyright 2023 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
#include <asm/io.h>
#include <rk_mini_dump.h>
/* don't modify it, it is behind pstore memory space */
#ifdef CONFIG_ROCKCHIP_MINIDUMP_SMEM_BASE
#define SMEM_BASE CONFIG_ROCKCHIP_MINIDUMP_SMEM_BASE
#else
#define SMEM_BASE 0x1f0000
#endif
#ifdef CONFIG_ROCKCHIP_MINIDUMP_MAX_ELF_SIZE
#define MAX_ELF_SIZE CONFIG_ROCKCHIP_MINIDUMP_MAX_ELF_SIZE
#else
#define MAX_ELF_SIZE 0x2000000
#endif
#ifdef CONFIG_ROCKCHIP_MINIDUMP_MAX_ENTRIES
#define MAX_NUM_ENTRIES (CONFIG_ROCKCHIP_MINIDUMP_MAX_ENTRIES + 1)
#else
#define MAX_NUM_ENTRIES 129
#endif
/* Bootloader has 16 byte support, 4 bytes reserved for itself */
#define MAX_REGION_NAME_LENGTH 16
#define MAX_STRTBL_SIZE (MAX_NUM_ENTRIES * MAX_REGION_NAME_LENGTH)
/**
* md_table : Local Minidump toc holder
* @num_regions : Number of regions requested
* @md_ss_toc : HLOS toc pointer
* @md_gbl_toc : Global toc pointer
* @md_regions : HLOS regions base pointer
* @entry : array of HLOS regions requested
*/
struct md_table {
u32 revision;
u32 num_regions;
struct md_ss_toc *md_ss_toc;
struct md_global_toc *md_gbl_toc;
struct md_ss_region *md_regions;
struct md_region entry[MAX_NUM_ENTRIES];
};
#define MAX_NUM_OF_SS 2
/**
* md_ss_toc: Sub system SMEM Table of content
* @md_ss_toc_init : SS toc init status
* @md_ss_enable_status : if set to 1, Bootloader would dump this SS regions
* @encryption_status: Encryption status for this subsystem
* @encryption_required : Decides to encrypt the SS regions or not
* @ss_region_count : Number of regions added in this SS toc
* @md_ss_smem_regions_baseptr : regions base pointer of the Subsystem
* @elf_header : base pointer of the minidump elf header
* @minidump_table : base pointer of the minidump_table
*/
struct md_ss_toc {
u32 md_ss_toc_init;
u32 md_ss_enable_status;
u32 encryption_status;
u32 encryption_required;
u32 ss_region_count;
u64 md_ss_smem_regions_baseptr;
u64 elf_header;
u64 elf_size;
u64 minidump_table;
};
/**
* md_global_toc: Global Table of Content
* @md_toc_init : Global Minidump init status
* @md_revision : Minidump revision
* @md_enable_status : Minidump enable status
* @md_ss_toc : Array of subsystems toc
*/
struct md_global_toc {
u32 md_toc_init;
u32 md_revision;
u32 md_enable_status;
struct md_ss_toc md_ss_toc[MAX_NUM_OF_SS];
};
/* Bootloader has 16 byte support, 4 bytes reserved for itself */
#define MAX_REGION_NAME_LENGTH 16
#define MD_REGION_VALID ('V' << 24 | 'A' << 16 | 'L' << 8 | 'I' << 0)
#define MD_REGION_INVALID ('I' << 24 | 'N' << 16 | 'V' << 8 | 'A' << 0)
#define MD_REGION_INIT ('I' << 24 | 'N' << 16 | 'I' << 8 | 'T' << 0)
#define MD_REGION_NOINIT 0
#define MD_SS_ENCR_REQ (0 << 24 | 'Y' << 16 | 'E' << 8 | 'S' << 0)
#define MD_SS_ENCR_NOTREQ (0 << 24 | 0 << 16 | 'N' << 8 | 'R' << 0)
#define MD_SS_ENCR_NONE ('N' << 24 | 'O' << 16 | 'N' << 8 | 'E' << 0)
#define MD_SS_ENCR_DONE ('D' << 24 | 'O' << 16 | 'N' << 8 | 'E' << 0)
#define MD_SS_ENCR_START ('S' << 24 | 'T' << 16 | 'R' << 8 | 'T' << 0)
#define MD_SS_ENABLED ('E' << 24 | 'N' << 16 | 'B' << 8 | 'L' << 0)
#define MD_SS_DISABLED ('D' << 24 | 'S' << 16 | 'B' << 8 | 'L' << 0)
#define EM_AARCH64 183 /* ARM 64 bit */
/**
* md_ss_region - Minidump region
* @name : Name of the region to be dumped
* @seq_num: : Use to differentiate regions with same name.
* @md_valid : This entry to be dumped (if set to 1)
* @region_base_address : Physical address of region to be dumped
* @region_size : Size of the region
*/
struct md_ss_region {
char name[MAX_REGION_NAME_LENGTH];
u32 seq_num;
u32 md_valid;
u64 region_base_address;
u64 region_size;
};
#define NO_FAULT_TAG 0x55aa55aa
static u32 no_fault;
static struct md_table *minidump_table;
u32 md_no_fault_handler(struct pt_regs *pt_regs, unsigned int esr)
{
if (no_fault == NO_FAULT_TAG) {
no_fault = 0;
return 1;
}
return 0;
}
#if defined(CONFIG_ROCKCHIP_RK3588)
static u32 md_is_ddr_addr(void *addr)
{
/* peripheral address space */
if (addr >= (void *)0xf0000000 && addr <= (void *)0x100000000)
return 0;
/* pcie address space */
if (addr > (void *)0x800000000)
return 0;
return 1;
}
#else
static u32 md_is_ddr_addr(void *addr)
{
return 1;
}
#endif
static u32 md_is_uboot_addr(void *addr)
{
volatile u32 *p_no_fault = &no_fault;
if(!md_is_ddr_addr(addr))
return 0;
*p_no_fault = NO_FAULT_TAG;
readb(addr);
return *p_no_fault;
}
struct md_region *md_get_region(char *name)
{
struct md_region *mdr;
int i, regno;
if (!md_is_uboot_addr((void *)minidump_table))
return NULL;
regno = minidump_table->num_regions;
for (i = 0; i < regno; i++) {
mdr = &minidump_table->entry[i];
if (!strcmp(mdr->name, name))
return mdr;
}
return NULL;
}
#ifdef CONFIG_ARM64
static Elf64_Xword rk_dump_elf64_image_phdr(void *ram_image,
Elf64_Addr ehaddr, Elf64_Xword ehsize)
{
Elf64_Ehdr *ehdr = (Elf64_Ehdr *)ehaddr;
Elf64_Phdr *phdr = NULL, *phdr_next = NULL;
Elf64_Shdr *shdr = NULL, *shdr_next = NULL;
unsigned int i = 0, error = 0, phdr_off = 0, strtbl_off = 0;
unsigned int size = 0, elf_size = ehsize;
if (!md_is_uboot_addr((void *)ehdr))
return 0;
if (!md_is_uboot_addr((void *)ram_image) ||
!md_is_uboot_addr((void *)ram_image + MAX_ELF_SIZE - 4))
return 0;
memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
ehdr->e_ident[EI_CLASS] = ELFCLASS64;
ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
ehdr->e_ident[EI_VERSION] = EV_CURRENT;
ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
if (ehdr->e_type != ET_CORE) {
error++;
ehdr->e_type = ET_CORE;
}
if (ehdr->e_machine != EM_AARCH64) {
error++;
ehdr->e_machine = EM_AARCH64;
}
if (ehdr->e_version != EV_CURRENT) {
error++;
ehdr->e_version = EV_CURRENT;
}
if (ehdr->e_ehsize != sizeof(*ehdr)) {
error++;
ehdr->e_ehsize = sizeof(*ehdr);
}
if (ehdr->e_phentsize != sizeof(*phdr)) {
error++;
ehdr->e_phentsize = sizeof(*phdr);
}
if (ehdr->e_shentsize != sizeof(*shdr)) {
error++;
ehdr->e_shentsize = sizeof(*shdr);
}
if (ehdr->e_shoff != sizeof(*ehdr)) {
error++;
ehdr->e_shoff = sizeof(*ehdr);
}
phdr_off = sizeof(*ehdr) + (sizeof(*shdr) * MAX_NUM_ENTRIES);
if (ehdr->e_phoff != phdr_off) {
error++;
ehdr->e_phoff = phdr_off;
}
printf("Minidump header error:0x%x\n", error);
/* If there are much error, maybe ehdr address is wrong */
if (error > 6)
return 0;
ehdr->e_shstrndx = 1;
phdr = (Elf64_Phdr *)(ehaddr + ehdr->e_phoff);
shdr = (Elf64_Shdr *)(ehaddr + ehdr->e_shoff);
shdr->sh_name = 0;
shdr->sh_type = 0;
shdr->sh_flags = 0;
shdr->sh_addr = 0;
shdr->sh_offset = 0;
shdr->sh_size = 0;
shdr->sh_link = 0;
shdr->sh_info = 0;
shdr->sh_addralign = 0;
shdr->sh_entsize = 0;
shdr++;
if (shdr->sh_name >= MAX_STRTBL_SIZE)
shdr->sh_name = 0;
shdr->sh_type = SHT_STRTAB;
shdr->sh_flags = 0;
shdr->sh_addr = 0;
shdr->sh_offset = phdr_off + (sizeof(*phdr) * MAX_NUM_ENTRIES);
shdr->sh_size = MAX_STRTBL_SIZE;
shdr->sh_link = 0;
shdr->sh_info = 0;
shdr->sh_addralign = 0;
shdr->sh_entsize = 0;
shdr++;
/* 3rd section is for minidump_table VA, used by parsers */
if (shdr->sh_name >= MAX_STRTBL_SIZE)
shdr->sh_name = 0;
shdr->sh_type = SHT_PROGBITS;
shdr->sh_flags = 0;
shdr->sh_offset = 0;
shdr->sh_size = 0;
shdr->sh_link = 0;
shdr->sh_info = 0;
shdr->sh_addralign = 0;
shdr->sh_entsize = 0;
shdr++;
shdr->sh_flags = 0;
shdr->sh_link = 0;
shdr->sh_info = 0;
shdr->sh_addralign = 0;
shdr->sh_entsize = 0;
strtbl_off = phdr_off + (sizeof(*phdr) * MAX_NUM_ENTRIES);
strtbl_off += MAX_STRTBL_SIZE;
if (phdr->p_offset != strtbl_off)
phdr->p_offset = strtbl_off;
if (shdr->sh_offset != strtbl_off)
shdr->sh_offset = strtbl_off;
phdr->p_filesz &= GENMASK(23, 0); /* 16MB */
phdr->p_memsz &= GENMASK(23, 0); /* 16MB */
shdr->sh_size &= GENMASK(23, 0); /* 16MB */
if (phdr->p_filesz == phdr->p_memsz) {
size = phdr->p_filesz;
shdr->sh_size = size;
} else if (phdr->p_filesz == shdr->sh_size) {
size = phdr->p_filesz;
phdr->p_memsz = size;
} else if (phdr->p_memsz == shdr->sh_size) {
size = phdr->p_memsz;
phdr->p_filesz = size;
} else {
printf("Minidump error first phdr p_filesz:0x%llx p_memsz:0x%llx sh_size:0x%llx\n",
phdr->p_filesz, phdr->p_memsz, shdr->sh_size);
return 0;
}
phdr++;
shdr++;
phdr_next = phdr + 1;
shdr_next = shdr + 1;
memset(ram_image, 0x0, 0x18000);
phdr->p_offset &= MAX_ELF_SIZE - 1;
shdr->sh_offset &= MAX_ELF_SIZE - 1;
elf_size &= MAX_ELF_SIZE - 1;
if (phdr->p_offset == shdr->sh_offset) {
elf_size = phdr->p_offset;
} else if (phdr->p_offset == elf_size) {
shdr->sh_offset = phdr->p_offset;
} else if (elf_size == shdr->sh_offset) {
phdr->p_offset = shdr->sh_offset;
} else {
printf("Minidump error phdr[1] p_offset:0x%llx sh_offset:0x%llx elf_size:0x%x\n",
phdr->p_offset, shdr->sh_offset, elf_size);
return 0;
}
/* save phdr space */
for (i = 1; i < MAX_NUM_ENTRIES; i++) {
void *src = NULL;
void *dst = NULL;
if (phdr->p_vaddr == 0 || shdr->sh_addr == 0)
break;
phdr->p_offset &= MAX_ELF_SIZE - 1;
shdr->sh_offset &= MAX_ELF_SIZE - 1;
if (phdr->p_offset != elf_size)
phdr->p_offset = elf_size;
if (shdr->sh_offset != elf_size)
shdr->sh_offset = elf_size;
phdr->p_paddr &= GENMASK(34, 0); /* 32GB */
phdr->p_align &= GENMASK(34, 0); /* 32GB */
shdr->sh_info &= GENMASK(34, 0); /* 32GB */
if (phdr->p_paddr != phdr->p_align && phdr->p_align == shdr->sh_entsize)
phdr->p_paddr = phdr->p_align;
phdr->p_type &= 0xf;
phdr->p_flags &= 0xf;
phdr->p_filesz &= GENMASK(23, 0); /* 16MB */
phdr->p_memsz &= GENMASK(23, 0); /* 16MB */
phdr->p_align = 0;
if (phdr->p_vaddr != shdr->sh_addr) {
if (shdr->sh_addr == shdr->sh_addralign)
phdr->p_vaddr = shdr->sh_addr;
else if (phdr->p_vaddr == shdr->sh_addralign)
shdr->sh_addr = phdr->p_vaddr;
else
printf("Minidump error phdr[%d] p_vaddr:0x%llx sh_addr:0x%llx sh_addralign:0x%llx\n",
i, phdr->p_vaddr, shdr->sh_addr, shdr->sh_addralign);
}
if (shdr->sh_name >= MAX_STRTBL_SIZE)
shdr->sh_name = 0;
shdr->sh_type = SHT_PROGBITS;
shdr->sh_flags = SHF_WRITE;
shdr->sh_size &= GENMASK(23, 0); /* 16MB */
shdr->sh_link = 0;
shdr->sh_info = 0;
shdr->sh_addralign = 0;
shdr->sh_entsize = 0;
if (phdr->p_filesz == phdr->p_memsz) {
size = phdr->p_filesz;
shdr->sh_size = size;
} else if (phdr->p_filesz == shdr->sh_size) {
size = phdr->p_filesz;
phdr->p_memsz = size;
} else if (phdr->p_memsz == shdr->sh_size) {
size = phdr->p_memsz;
phdr->p_filesz = size;
} else {
if ((phdr_next->p_offset == shdr_next->sh_offset) &&
(phdr_next->p_offset != 0)) {
size = phdr_next->p_offset - phdr->p_offset;
phdr->p_filesz = size;
phdr->p_memsz = size;
shdr->sh_size = size;
} else {
printf("Minidump error phdr[%d] p_filesz:0x%llx p_memsz:0x%llx sh_size:0x%llx",
i, phdr->p_filesz, phdr->p_memsz, shdr->sh_size);
printf("p_offset:0x%llx sh_offset:0x%llx\n", phdr_next->p_offset,
shdr_next->sh_offset);
return 0;
}
}
elf_size += size;
src = (void *)(Elf64_Addr)phdr->p_paddr;
dst = ram_image + phdr->p_offset;
if (size > MAX_ELF_SIZE / 2)
goto donot_cpy;
if (!md_is_uboot_addr(src) || !md_is_uboot_addr(src + size - 1)) {
printf("Minidump error src 0x%p-0x%p\n", src, src + size - 1);
goto donot_cpy;
}
if (!md_is_uboot_addr(dst) || !md_is_uboot_addr(dst + size - 1)) {
printf("Minidump error dst 0x%p-0x%p\n", dst, dst + size - 1);
goto donot_cpy;
}
if (size)
memcpy(dst, src, size);
donot_cpy:
phdr++;
shdr++;
phdr_next++;
shdr_next++;
}
if (ehdr->e_phnum != i)
ehdr->e_phnum = i;
if ((ehdr->e_phnum + 3) != ehdr->e_shnum)
ehdr->e_shnum = ehdr->e_phnum + 3;
/* copy ehdr to ram image */
memcpy(ram_image, (void *)ehdr, ehsize);
flush_cache((unsigned long)ram_image, elf_size);
printf("Minidump.elf 0x%x@0x%p\n", elf_size, ram_image);
return elf_size;
}
#else
static Elf32_Word rk_dump_elf32_image_phdr(void *ram_image, Elf32_Addr ehaddr,
Elf32_Word ehsize)
{
Elf32_Ehdr *ehdr = (Elf32_Ehdr *)ehaddr;
Elf32_Phdr *phdr = (Elf32_Phdr *)(ehaddr + ehdr->e_phoff);
Elf32_Word ram_image_size = 0;
int i;
/* copy ehdr to ram image */
memcpy(ram_image, (void *)ehdr, ehsize);
/* save phdr space */
for (i = 0; i < ehdr->e_phnum; ++i) {
void *src = (void *)(Elf32_Addr)phdr->p_paddr;
void *dst = ram_image + phdr->p_offset;
if (phdr->p_filesz)
memcpy(dst, src, phdr->p_filesz);
if (phdr->p_filesz != phdr->p_memsz)
memset(dst + phdr->p_filesz, 0x00,
phdr->p_memsz - phdr->p_filesz);
++phdr;
}
phdr--;
ram_image_size = phdr->p_memsz + phdr->p_offset;
printf("Minidump.elf 0x%llx@0x%p\n", ram_image_size, ram_image);
return ram_image_size;
}
#endif
void rk_minidump_init(void)
{
struct md_global_toc *mdg_toc = (struct md_global_toc *)SMEM_BASE;
struct md_ss_toc *md_ss_toc = &mdg_toc->md_ss_toc[0];
struct md_ss_region *mdreg;
printf("Minidump: init...\n");
mdg_toc->md_toc_init = 1;
mdg_toc->md_revision = 1;
mdg_toc->md_enable_status = 0;
if (md_ss_toc->md_ss_enable_status == MD_SS_ENABLED) {
/* linux would set it 1, so we set it 0 here */
md_ss_toc->md_ss_enable_status = 0;
flush_cache((unsigned long)md_ss_toc, 8);
mdreg = (struct md_ss_region *)md_ss_toc->md_ss_smem_regions_baseptr;
minidump_table = (struct md_table *)md_ss_toc->minidump_table;
#ifdef CONFIG_ARM64
md_ss_toc->elf_size = rk_dump_elf64_image_phdr((void *)md_ss_toc->elf_header,
(Elf64_Addr)mdreg->region_base_address,
(Elf64_Xword)mdreg->region_size);
#else
md_ss_toc->elf_size = rk_dump_elf32_image_phdr((void *)md_ss_toc->elf_header,
(Elf32_Addr)mdreg->region_base_address,
(Elf32_Word)mdreg->region_size);
#endif
}
}
#ifdef CONFIG_ARM64
void rk_minidump_get_el64(void **ram_image_addr, Elf64_Xword *ram_image_size)
{
struct md_global_toc *mdg_toc = (struct md_global_toc *)SMEM_BASE;
struct md_ss_toc *md_ss_toc = &mdg_toc->md_ss_toc[0];
*ram_image_addr = (void *)md_ss_toc->elf_header;
*ram_image_size = md_ss_toc->elf_size;
}
#else
void rk_minidump_get_el32(void **ram_image_addr, Elf32_Word *ram_image_size)
{
struct md_global_toc *mdg_toc = (struct md_global_toc *)SMEM_BASE;
struct md_ss_toc *md_ss_toc = &mdg_toc->md_ss_toc[0];
*ram_image_addr = (void *)md_ss_toc->elf_header;
*ram_image_size = md_ss_toc->elf_size;
}
#endif

25
u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c
View File

@ -404,9 +404,32 @@ void board_debug_uart_init(void)
#endif
}
#ifdef CONFIG_SUPPORT_USBPLUG
void board_set_iomux(enum if_type if_type, int devnum, int routing)
{
switch (if_type) {
case IF_TYPE_MMC:
/* emmc iomux */
writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
writel(0x00ff0011, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
break;
case IF_TYPE_MTD:
/* fspi iomux */
writel(0x0f000700, GPIO4_IOC_BASE + 0x0030);
writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);
writel(0x0f0f0202, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);
writel(0x00ff0022, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);
break;
default:
break;
}
}
#endif
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
/* Save chip version to OS_REG1[2:0] */
if (readl(ROM_VER_REG) == ROM_V2)
writel((readl(CHIP_VER_REG) & ~CHIP_VER_MSK) | V(2), CHIP_VER_REG);

61
u-boot/arch/arm/mach-rockchip/spl.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <version.h>
#include <boot_rkimg.h>
#include <debug_uart.h>
#include <dm.h>
@ -153,7 +154,7 @@ void *memset(void *s, int c, size_t count)
#ifdef CONFIG_SPL_DM_RESET
static void brom_download(void)
{
if (debug_uart_tstc() && debug_uart_getc() == 0x02) {
if (gd->console_evt == 0x02) {
printf("ctrl+b: Bootrom download!\n");
writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
do_reset(NULL, 0, 0, NULL);
@ -161,6 +162,30 @@ static void brom_download(void)
}
#endif
static void spl_hotkey_init(void)
{
/* If disable console, skip getting uart reg */
if (!gd || gd->flags & GD_FLG_DISABLE_CONSOLE)
return;
if (!gd->have_console)
return;
/* serial uclass only exists when enable CONFIG_SPL_FRAMEWORK */
#ifdef CONFIG_SPL_FRAMEWORK
if (serial_tstc()) {
gd->console_evt = serial_getc();
#else
if (debug_uart_tstc()) {
gd->console_evt = debug_uart_getc();
#endif
if (gd->console_evt <= 0x1a) /* 'z' */
printf("SPL Hotkey: ctrl+%c\n",
gd->console_evt + 'a' - 1);
}
return;
}
void board_init_f(ulong dummy)
{
#ifdef CONFIG_SPL_FRAMEWORK
@ -209,12 +234,14 @@ void board_init_f(ulong dummy)
/* Some SoCs like rk3036 does not use any frame work */
sdram_init();
#endif
/* Get hotkey and store in gd */
spl_hotkey_init();
#ifdef CONFIG_SPL_DM_RESET
brom_download();
#endif
arch_cpu_init();
rk_board_init_f();
#ifdef CONFIG_SPL_RAM_DEVICE
#if defined(CONFIG_SPL_RAM_DEVICE) && defined(CONFIG_SPL_PCIE_EP_SUPPORT)
rockchip_pcie_ep_get_firmware();
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
@ -329,6 +356,9 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
{
#ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device);
#ifdef BUILD_SPL_TAG
atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG);
#endif
#endif
return;
}
@ -365,16 +395,27 @@ bool spl_is_low_power(void)
void spl_next_stage(struct spl_image_info *spl)
{
const char *reason[] = { "Recovery key", "Ctrl+c", "LowPwr", "Unknown" };
uint32_t reg_boot_mode;
int i = 0;
if (spl_rockchip_dnl_key_pressed()) {
i = 0;
spl->next_stage = SPL_NEXT_STAGE_UBOOT;
return;
goto out;
}
if (gd->console_evt == 0x03) {
i = 1;
spl->next_stage = SPL_NEXT_STAGE_UBOOT;
goto out;
}
#ifdef CONFIG_SPL_DM_FUEL_GAUGE
if (spl_is_low_power()) {
i = 2;
spl->next_stage = SPL_NEXT_STAGE_UBOOT;
return;
goto out;
}
#endif
@ -388,11 +429,19 @@ void spl_next_stage(struct spl_image_info *spl)
spl->next_stage = SPL_NEXT_STAGE_KERNEL;
break;
default:
if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG)
if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG) {
spl->next_stage = SPL_NEXT_STAGE_KERNEL;
else
} else {
i = 3;
spl->next_stage = SPL_NEXT_STAGE_UBOOT;
}
}
out:
if (spl->next_stage == SPL_NEXT_STAGE_UBOOT)
printf("Enter uboot reason: %s\n", reason[i]);
return;
}
#endif

109
u-boot/arch/arm/mach-rockchip/spl_pcie_ep_boot.c
View File

@ -186,6 +186,7 @@ static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags)
static void pcie_bar_init(void *dbi_base)
{
void *resbar_base;
u32 val;
writel(0, dbi_base + 0x10);
writel(0, dbi_base + 0x14);
@ -194,15 +195,20 @@ static void pcie_bar_init(void *dbi_base)
writel(0, dbi_base + 0x20);
writel(0, dbi_base + 0x24);
/* Disable ASPM */
val = readl(dbi_base + 0x7c);
val &= ~(3 << 10);
writel(val, dbi_base + 0x7c);
/* Resize BAR0 to support 4M 32bits */
resbar_base = dbi_base + PCI_RESBAR;
writel(0xfffff0, resbar_base + 0x4);
writel(0x40, resbar_base + 0x4);
writel(0x2c0, resbar_base + 0x8);
/* BAR2: 64M 64bits */
writel(0xfffff0, resbar_base + 0x14);
writel(0x400, resbar_base + 0x14);
writel(0x6c0, resbar_base + 0x18);
/* BAR4: Fixed for EP wired register, 1M 32bits */
writel(0xfffff0, resbar_base + 0x24);
writel(0x10, resbar_base + 0x24);
writel(0xc0, resbar_base + 0x28);
/* Set flags */
rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32);
@ -333,7 +339,7 @@ static void pcie_update_atags(void)
struct tag_ram_partition t_ram_part;
if (!atags_is_available()) {
printf("RKEP: No ATAGS data found, create new!\n");
printep("RKEP: No ATAGS data found, create new!\n");
atags_destroy();
}
@ -401,7 +407,27 @@ static void pcie_board_init(void)
#define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0
#define FIREWALL_PCIE_ACCESS 0xfe586040
#define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38)
#define PMU1_GRF_BASE 0xfd58a000
#define PMU_PWR_GATE_SFTCON1 0xfd8d8150
#define PMU1_IOC_BASE 0xfd5F0000
#define CRU_GLB_RST_CON_OFFSET (0xC10U)
#define CRU_GLB_SRST_FST_VALUE_OFFSET (0xC08U)
void pcie_first_reset(void)
{
printep("Fst Reset\n");
mdelay(1);
writel(0xFFDF, CRU_BASE_ADDR + CRU_GLB_RST_CON_OFFSET);
writel(0xffffffff, PMU1_GRF_BASE + 0x4); // reset width
writel(0x30003000, PMU1_GRF_BASE + 0x1c); // pmu1_grf pmu1_ioc hiold
writel(0x00f00020, PMU1_IOC_BASE + 0x0); //select tsad_shut_m0 iomux
writel(0xFDB9, CRU_BASE_ADDR + CRU_GLB_SRST_FST_VALUE_OFFSET);
while (1)
;
}
static void pcie_cru_init(void)
{
u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0;
@ -463,7 +489,7 @@ static void pcie_cru_init(void)
phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04);
if (phy0_mplla != t0 || phy1_mplla != t1) {
printf("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla);
printep("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla);
t0 = phy0_mplla;
t1 = phy1_mplla;
@ -474,8 +500,17 @@ static void pcie_cru_init(void)
udelay(10);
}
/* PHY config: no config need for snps3.0phy */
if (i >= timeout) {
printep("lock fail\n");
mdelay(1);
pcie_first_reset();
}
/* PHY config: no config need for snps3.0phy */
}
static void pcie_firewall_init(void)
{
/* Enable PCIe Access in firewall and master secure mode */
writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC);
writel(0x01800000, FIREWALL_PCIE_ACCESS);
@ -509,13 +544,31 @@ static const u16 phy_fw[] = {
#define CRU_GATE_CON33 (CRU_BASE + 0x384)
#define CRU_SOFTRST_CON12 (CRU_BASE + 0x430)
#define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c)
#define CRU_GLB_SRST_FST_OFFSET (0xD4U)
#define PCIE30_PHY_GRF 0xFDCB8000
#define SYS_GRF_BASE 0xFDC60000
void pcie_first_reset(void)
{
printep("Fst Reset\n");
mdelay(1);
writel(0x00040004, CRU_BASE + 0x104);
writel(0x00700010, CRU_BASE);
writel(0x00100010, SYS_GRF_BASE + 0x508);
writel(0xFDB9, CRU_BASE + CRU_GLB_SRST_FST_OFFSET);
while (1)
;
}
void pcie_cru_init(void)
{
u32 i, reg;
u32 i, reg, timeout = 500;
void __iomem *mmio = (void __iomem *)0xFE8C0000;
u32 phy0_status0, phy0_status1, t0 = 0, t1 = 0;
/* Enable phy and controoler clk */
writel(0xffff0000, PMUCRU_PMUGATE_CON02);
@ -548,20 +601,20 @@ void pcie_cru_init(void)
writel(0x40000000, CRU_SOFTRST_CON27);
udelay(5);
printf("RKEP: sram initial\n");
printep("RKEP: sram initial\n");
while (1) {
reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0);
if (RK3568_SRAM_INIT_DONE(reg))
break;
}
printf("RKEP: sram init done\n");
printep("RKEP: sram init done\n");
writel((0x3 << 8) | (0x3 << (8 + 16)),
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
writel(phy_fw[i], mmio + (i << 2));
printf("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
printep("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
writel((0x0 << 8) | (0x3 << (8 + 16)),
PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
writel((0x1 << 14) | (0x1 << (14 + 16)),
@ -570,8 +623,35 @@ void pcie_cru_init(void)
writel(0xffff0000, CRU_SOFTRST_CON12);
writel(0x100010, PCIE_SNPS_APB_BASE + 0x180);
/* S-Phy: waiting for phy locked */
for (i = 0; i < timeout; i++) {
phy0_status0 = readl(PCIE30_PHY_GRF + 0x80);
phy0_status1 = readl(PCIE30_PHY_GRF + 0x84);
if (phy0_status0 != t0 || phy0_status1 != t1) {
printep("RKEP: GRF:0x80=%x, 0x84=%x...\n", phy0_status0, phy0_status1);
t0 = phy0_status0;
t1 = phy0_status1;
if (RK3568_SRAM_INIT_DONE(phy0_status0))
break;
}
udelay(10);
}
if (i >= timeout) {
printep("lock fail\n");
mdelay(1);
pcie_first_reset();
}
udelay(1);
}
static void pcie_firewall_init(void)
{
}
#endif
static void pcie_ep_init(void)
@ -627,6 +707,12 @@ reinit:
val = readl(dbi_base + 0x4);
writel(val | 0x6, dbi_base + 0x4);
val = readl(apb_base + 0x10);
if (val & 0x4) {
printep("Link is reset, int status misc=%x\n", val);
retries++;
}
if (retries) /* Set app_dly2_done to enable app_ltssm_enable */
writel(0x80008, apb_base + 0x180);
else /* Enable LTSSM */
@ -674,10 +760,13 @@ void rockchip_pcie_ep_init(void)
writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
udelay(10);
#endif
pcie_firewall_init();
/* Re-in pcie initial */
val = readl(PCIE_SNPS_APB_BASE + 0x300);
if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) {
printf("RKEP: already link up\n");
pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP);
return;
}

125
u-boot/arch/arm/mach-rockchip/usbplug.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2020 Rockchip Electronics Co., Ltd.
* (C) Copyright 2020-2023 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -12,46 +12,127 @@
DECLARE_GLOBAL_DATA_PTR;
struct bootdev_list {
u32 if_type;
u8 devnum;
u8 iomux_routing;
};
#if CONFIG_IS_ENABLED(ROCKCHIP_RK3588)
static const struct bootdev_list dev_list[] = {
{IF_TYPE_MMC, 0, 0},
{IF_TYPE_MTD, 0, 0}, /* BLK_MTD_NAND */
{IF_TYPE_MTD, 1, 0}, /* BLK_MTD_SPI_NAND FSPI M0 */
{IF_TYPE_MTD, 1, 1}, /* BLK_MTD_SPI_NAND FSPI M1 */
{IF_TYPE_MTD, 1, 2}, /* BLK_MTD_SPI_NAND FSPI M2 */
{IF_TYPE_MTD, 2, 0}, /* BLK_MTD_SPI_NOR FSPI M0 */
{IF_TYPE_MTD, 2, 1}, /* BLK_MTD_SPI_NOR FSPI M1 */
{IF_TYPE_MTD, 2, 2}, /* BLK_MTD_SPI_NOR FSPI M2 */
{IF_TYPE_RKNAND, 2, 0},
};
#else
static const struct bootdev_list dev_list[] = {
{IF_TYPE_MMC, 0, 0},
{IF_TYPE_MTD, 0, 0}, /* BLK_MTD_NAND */
{IF_TYPE_MTD, 1, 0}, /* BLK_MTD_SPI_NAND */
{IF_TYPE_MTD, 2, 0}, /* BLK_MTD_SPI_NOR */
{IF_TYPE_RKNAND, 0, 0},
};
#endif
static struct blk_desc *boot_blk_desc;
struct blk_desc *rockchip_get_bootdev(void)
{
return boot_blk_desc;
}
__weak void board_set_iomux(enum if_type if_type, int devnum, int routing)
{
}
struct blk_desc *usbplug_blk_get_devnum_by_type(enum if_type if_type, int devnum)
{
struct blk_desc *blk_desc = NULL;
u8 iomux_routing;
int i = 0;
for (i = 0; i < ARRAY_SIZE(dev_list); i++) {
if (if_type != dev_list[i].if_type || devnum != dev_list[i].devnum)
continue;
iomux_routing = dev_list[i].iomux_routing;
switch (if_type) {
#ifdef CONFIG_MMC
case IF_TYPE_MMC:
board_set_iomux(if_type, devnum, iomux_routing);
mmc_initialize(gd->bd);
break;
#endif
case IF_TYPE_MTD:
board_set_iomux(if_type, devnum, iomux_routing);
break;
default:
printf("Bootdev 0x%x is not support\n", if_type);
return NULL;
}
printf("scandev: %s %d m%d\n", blk_get_if_type_name(if_type), devnum, iomux_routing);
blk_desc = blk_get_devnum_by_type(if_type, devnum);
if (blk_desc)
break;
}
boot_blk_desc = blk_desc;
return blk_desc;
}
static char *bootdev_rockusb_cmd(void)
{
const char *devtype, *devnum;
const char *bootdev_list[] = {
"mmc", "0",
"mtd", "0",
"mtd", "1",
"mtd", "2",
"rknand", "0",
NULL, NULL,
};
struct blk_desc *blk_desc = NULL;
u32 if_type = IF_TYPE_UNKNOWN;
u8 devnum, iomux_routing;
char *cmd;
int i = 0;
devtype = bootdev_list[0];
devnum = bootdev_list[1];
while (devtype) {
if (!strcmp("mmc", devtype))
for (i = 0; i < ARRAY_SIZE(dev_list); i++) {
if_type = dev_list[i].if_type;
devnum = dev_list[i].devnum;
iomux_routing = dev_list[i].iomux_routing;
switch (if_type) {
#ifdef CONFIG_MMC
case IF_TYPE_MMC:
board_set_iomux(if_type, devnum, iomux_routing);
mmc_initialize(gd->bd);
if (blk_get_devnum_by_typename(devtype, atoi(devnum)))
break;
#endif
case IF_TYPE_MTD:
board_set_iomux(if_type, devnum, iomux_routing);
break;
default:
printf("Bootdev 0x%x is not support\n", if_type);
return NULL;
}
i += 2;
devtype = bootdev_list[i];
devnum = bootdev_list[i + 1];
printf("Scandev: %s %d m%d\n", blk_get_if_type_name(if_type), devnum, iomux_routing);
blk_desc = blk_get_devnum_by_type(if_type, devnum);
if (blk_desc)
break;
}
if (!devtype) {
boot_blk_desc = blk_desc;
if (!if_type) {
printf("No boot device\n");
return NULL;
}
printf("Bootdev: %s %s\n", devtype, devnum);
printf("Bootdev: %s %d\n", blk_get_if_type_name(if_type), devnum);
cmd = malloc(32);
if (!cmd)
return NULL;
snprintf(cmd, 32, "rockusb 0 %s %s", devtype, devnum);
snprintf(cmd, 32, "rockusb 0 %s %d", blk_get_if_type_name(if_type), devnum);
return cmd;
}

40
u-boot/arch/arm/mach-rockchip/vendor.c
View File

@ -11,6 +11,7 @@
#include <nand.h>
#include <part.h>
#include <fdt_support.h>
#include <usbplug.h>
/* tag for vendor check */
#define VENDOR_TAG 0x524B5644
@ -649,10 +650,10 @@ int vendor_storage_read(u16 id, void *pbuf, u16 size)
*/
int vendor_storage_write(u16 id, void *pbuf, u16 size)
{
int cnt, ret = 0;
u32 i, next_index, align_size;
struct vendor_item *item;
u32 i, j, next_index, align_size, alloc_size, next_size;
u16 part_size, max_item_num, offset, part_num;
struct vendor_item *item;
int cnt, ret = 0;
/* init vendor storage */
if (!bootdev_type) {
@ -703,10 +704,35 @@ int vendor_storage_write(u16 id, void *pbuf, u16 size)
/* If item already exist, update the item data */
for (i = 0; i < vendor_info.hdr->item_num; i++) {
if ((item + i)->id == id) {
debug("[Vendor INFO]:Find the matching item, id=%d\n", id);
offset = (item + i)->offset;
memcpy((vendor_info.data + offset), pbuf, size);
(item + i)->size = size;
alloc_size = ((item + i)->size + VENDOR_BTYE_ALIGN) & (~VENDOR_BTYE_ALIGN);
if (size > alloc_size) {
if (vendor_info.hdr->free_size < align_size)
return -EINVAL;
debug("[Vendor INFO]:Find the matching item, id=%d and resize\n", id);
offset = (item + i)->offset;
for (j = i; j < vendor_info.hdr->item_num - 1; j++) {
(item + j)->id = (item + j + 1)->id;
(item + j)->size = (item + j + 1)->size;
(item + j)->offset = offset;
next_size = ((item + j + 1)->size + VENDOR_BTYE_ALIGN) & (~VENDOR_BTYE_ALIGN);
memcpy((vendor_info.data + offset),
(vendor_info.data + (item + j + 1)->offset),
next_size);
offset += next_size;
}
(item + j)->id = id;
(item + j)->offset = offset;
(item + j)->size = size;
memcpy((vendor_info.data + offset), pbuf, size);
vendor_info.hdr->free_offset = offset + align_size;
vendor_info.hdr->free_size -= align_size - alloc_size;
} else {
debug("[Vendor INFO]:Find the matching item, id=%d\n", id);
offset = (item + i)->offset;
memcpy((vendor_info.data + offset), pbuf, size);
(item + i)->size = size;
}
vendor_info.hdr->version++;
*(vendor_info.version2) = vendor_info.hdr->version;
vendor_info.hdr->next_index++;

3
u-boot/arch/arm/mach-rockchip/vendor_misc.c
View File

@ -19,6 +19,7 @@ struct hdcpdata {
unsigned char data[0];
};
#ifndef CONFIG_SUPPORT_USBPLUG
int vendor_handle_hdcp(struct vendor_item *vhead)
{
struct arm_smccc_res res;
@ -61,4 +62,4 @@ int vendor_handle_hdcp(struct vendor_item *vhead)
return 0;
}
#endif

56
u-boot/board/rockchip/evb_rk3528/evb_rk3528.c
View File

@ -7,27 +7,79 @@
#include <common.h>
#include <dwc3-uboot.h>
#include <usb.h>
#include <linux/usb/phy-rockchip-naneng-combphy.h>
#include <asm/io.h>
#include <rockusb.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_DWC3
#define CRU_BASE 0xff4a0000
#define CRU_SOFTRST_CON33 0x0a84
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.maximum_speed = USB_SPEED_SUPER,
.base = 0xfe500000,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
.dis_u2_susphy_quirk = 1,
.dis_u1u2_quirk = 1,
.usb2_phyif_utmi_width = 16,
};
int usb_gadget_handle_interrupts(void)
int usb_gadget_handle_interrupts(int index)
{
dwc3_uboot_handle_interrupt(0);
return 0;
}
bool rkusb_usb3_capable(void)
{
return true;
}
static void usb_reset_otg_controller(void)
{
writel(0x00020002, CRU_BASE + CRU_SOFTRST_CON33);
mdelay(1);
writel(0x00020000, CRU_BASE + CRU_SOFTRST_CON33);
mdelay(1);
}
int board_usb_init(int index, enum usb_init_type init)
{
u32 ret = 0;
usb_reset_otg_controller();
#if defined(CONFIG_SUPPORT_USBPLUG)
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
if (rkusb_switch_usb3_enabled()) {
dwc3_device_data.maximum_speed = USB_SPEED_SUPER;
ret = rockchip_combphy_usb3_uboot_init();
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
}
}
#else
ret = rockchip_combphy_usb3_uboot_init();
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
}
#endif
return dwc3_uboot_init(&dwc3_device_data);
}
#if defined(CONFIG_SUPPORT_USBPLUG)
int board_usb_cleanup(int index, enum usb_init_type init)
{
dwc3_uboot_exit(index);
return 0;
}
#endif
#endif

56
u-boot/board/rockchip/evb_rk3588/evb_rk3588.c
View File

@ -7,27 +7,79 @@
#include <common.h>
#include <dwc3-uboot.h>
#include <usb.h>
#include <linux/usb/phy-rockchip-usbdp.h>
#include <asm/io.h>
#include <rockusb.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_DWC3
#define CRU_BASE 0xfd7c0000
#define CRU_SOFTRST_CON42 0x0aa8
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.maximum_speed = USB_SPEED_SUPER,
.base = 0xfc000000,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
.dis_u2_susphy_quirk = 1,
.dis_u1u2_quirk = 1,
.usb2_phyif_utmi_width = 16,
};
int usb_gadget_handle_interrupts(void)
int usb_gadget_handle_interrupts(int index)
{
dwc3_uboot_handle_interrupt(0);
return 0;
}
bool rkusb_usb3_capable(void)
{
return true;
}
static void usb_reset_otg_controller(void)
{
writel(0x00100010, CRU_BASE + CRU_SOFTRST_CON42);
mdelay(1);
writel(0x00100000, CRU_BASE + CRU_SOFTRST_CON42);
mdelay(1);
}
int board_usb_init(int index, enum usb_init_type init)
{
u32 ret = 0;
usb_reset_otg_controller();
#if defined(CONFIG_SUPPORT_USBPLUG)
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
if (rkusb_switch_usb3_enabled()) {
dwc3_device_data.maximum_speed = USB_SPEED_SUPER;
ret = rockchip_u3phy_uboot_init();
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
}
}
#else
ret = rockchip_u3phy_uboot_init();
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
}
#endif
return dwc3_uboot_init(&dwc3_device_data);
}
#if defined(CONFIG_SUPPORT_USBPLUG)
int board_usb_cleanup(int index, enum usb_init_type init)
{
dwc3_uboot_exit(index);
return 0;
}
#endif
#endif

9
u-boot/cmd/Kconfig
View File

@ -929,6 +929,15 @@ config CMD_PCMCIA
about 1990. These devices are typically removable memory or network
cards using a standard 68-pin connector.
config CMD_PINMUX
bool "pinmux - show pins muxing"
depends on PINCTRL
default y if PINCTRL
help
Parse all available pin-controllers and show pins muxing. This
is useful for debug purpoer to check the pin muxing and to know if
a pin is configured as a GPIO or as an alternate function.
config CMD_READ
bool "read - Read binary data from a partition"
help

1
u-boot/cmd/Makefile
View File

@ -113,6 +113,7 @@ ifdef CONFIG_PCI
obj-$(CONFIG_CMD_PCI) += pci.o
endif
obj-y += pcmcia.o
obj-$(CONFIG_CMD_PINMUX) += pinmux.o
obj-$(CONFIG_CMD_PXE) += pxe.o
obj-$(CONFIG_CMD_QFW) += qfw.o
obj-$(CONFIG_CMD_READ) += read.o

8
u-boot/cmd/atags.c
View File

@ -179,6 +179,14 @@ static void atags_print_tag(struct tag *t)
for (i = 0; i < ARRAY_SIZE(t->u.pstore.buf); i++)
printf(" table[%d] = 0x%x@0x%x\n", i, t->u.pstore.buf[i].size, t->u.pstore.buf[i].addr);
break;
case ATAG_FWVER:
printf("[fwver]:\n");
printf(" magic = 0x%x\n", t->hdr.magic);
printf(" size = 0x%x\n\n", t->hdr.size << 2);
printf(" version = 0x%x\n", t->u.fwver.version);
for (i = 0; i < FW_MAX; i++)
printf(" ver[%d] = %s\n", i, t->u.fwver.ver[i]);
break;
default:
printf("%s: magic(%x) is not support\n", __func__, t->hdr.magic);
}

5
u-boot/cmd/demo.c
View File

@ -67,9 +67,8 @@ int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
puts("Demo uclass entries:\n");
for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev);
dev;
ret = uclass_next_device(&dev)) {
for (i = 0, uclass_first_device(UCLASS_DEMO, &dev); dev;
uclass_next_device(&dev)) {
printf("entry %d - instance %08x, ops %08x, platdata %08x\n",
i++, map_to_sysmem(dev),
map_to_sysmem(dev->driver->ops),

7
u-boot/cmd/gpio.c
View File

@ -68,14 +68,13 @@ static int do_gpio_status(bool all, const char *gpio_name)
struct udevice *dev;
int banklen;
int flags;
int ret;
flags = 0;
if (gpio_name && !*gpio_name)
gpio_name = NULL;
for (ret = uclass_first_device(UCLASS_GPIO, &dev);
for (uclass_first_device(UCLASS_GPIO, &dev);
dev;
ret = uclass_next_device(&dev)) {
uclass_next_device(&dev)) {
const char *bank_name;
int num_bits;
@ -111,7 +110,7 @@ static int do_gpio_status(bool all, const char *gpio_name)
flags |= FLAG_SHOW_NEWLINE;
}
return ret;
return 0;
}
#endif

147
u-boot/cmd/pinmux.c Normal file
View File

@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
#include <command.h>
#include <dm.h>
#include <errno.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
#define LIMIT_DEVNAME 30
static struct udevice *currdev;
static int do_dev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *name;
int ret;
switch (argc) {
case 2:
name = argv[1];
ret = uclass_get_device_by_name(UCLASS_PINCTRL, name, &currdev);
if (ret) {
printf("Can't get the pin-controller: %s!\n", name);
return CMD_RET_FAILURE;
}
/* fall through */
case 1:
if (!currdev) {
printf("Pin-controller device is not set!\n");
return CMD_RET_USAGE;
}
printf("dev: %s\n", currdev->name);
}
return CMD_RET_SUCCESS;
}
static int show_pinmux(struct udevice *dev)
{
char pin_name[PINNAME_SIZE];
char pin_mux[PINMUX_SIZE];
int pins_count;
int i;
int ret;
pins_count = pinctrl_get_pins_count(dev);
if (pins_count == -ENOSYS) {
printf("Ops get_pins_count not supported\n");
return pins_count;
}
for (i = 0; i < pins_count; i++) {
ret = pinctrl_get_pin_name(dev, i, pin_name, PINNAME_SIZE);
if (ret == -ENOSYS) {
printf("Ops get_pin_name not supported\n");
return ret;
}
ret = pinctrl_get_pin_muxing(dev, i, pin_mux, PINMUX_SIZE);
if (ret) {
printf("Ops get_pin_muxing error (%d)\n", ret);
return ret;
}
printf("%-*s: %-*s\n", PINNAME_SIZE, pin_name,
PINMUX_SIZE, pin_mux);
}
return 0;
}
static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
int ret = CMD_RET_USAGE;
if (currdev && (argc < 2 || strcmp(argv[1], "-a")))
return show_pinmux(currdev);
if (argc < 2 || strcmp(argv[1], "-a"))
return ret;
uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
/* insert a separator between each pin-controller display */
printf("--------------------------\n");
printf("%s:\n", dev->name);
ret = show_pinmux(dev);
if (ret < 0)
printf("Can't display pin muxing for %s\n",
dev->name);
}
return ret;
}
static int do_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
printf("| %-*.*s| %-*.*s| %s\n",
LIMIT_DEVNAME, LIMIT_DEVNAME, "Device",
LIMIT_DEVNAME, LIMIT_DEVNAME, "Driver",
"Parent");
uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
printf("| %-*.*s| %-*.*s| %s\n",
LIMIT_DEVNAME, LIMIT_DEVNAME, dev->name,
LIMIT_DEVNAME, LIMIT_DEVNAME, dev->driver->name,
dev->parent->name);
}
return CMD_RET_SUCCESS;
}
static cmd_tbl_t pinmux_subcmd[] = {
U_BOOT_CMD_MKENT(dev, 2, 1, do_dev, "", ""),
U_BOOT_CMD_MKENT(list, 1, 1, do_list, "", ""),
U_BOOT_CMD_MKENT(status, 2, 1, do_status, "", ""),
};
static int do_pinmux(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
cmd_tbl_t *cmd;
argc--;
argv++;
cmd = find_cmd_tbl(argv[0], pinmux_subcmd, ARRAY_SIZE(pinmux_subcmd));
if (!cmd || argc > cmd->maxargs)
return CMD_RET_USAGE;
return cmd->cmd(cmdtp, flag, argc, argv);
}
U_BOOT_CMD(pinmux, CONFIG_SYS_MAXARGS, 1, do_pinmux,
"show pin-controller muxing",
"list - list UCLASS_PINCTRL devices\n"
"pinmux dev [pincontroller-name] - select pin-controller device\n"
"pinmux status [-a] - print pin-controller muxing [for all]\n"
)

11
u-boot/cmd/pmic.c
View File

@ -50,27 +50,20 @@ static int do_dev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int do_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
int ret;
printf("| %-*.*s| %-*.*s| %s @ %s\n",
LIMIT_DEV, LIMIT_DEV, "Name",
LIMIT_PARENT, LIMIT_PARENT, "Parent name",
"Parent uclass", "seq");
for (ret = uclass_first_device(UCLASS_PMIC, &dev); dev;
ret = uclass_next_device(&dev)) {
if (ret)
continue;
for (uclass_first_device(UCLASS_PMIC, &dev); dev;
uclass_next_device(&dev)) {
printf("| %-*.*s| %-*.*s| %s @ %d\n",
LIMIT_DEV, LIMIT_DEV, dev->name,
LIMIT_PARENT, LIMIT_PARENT, dev->parent->name,
dev_get_uclass_name(dev->parent), dev->parent->seq);
}
if (ret)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}

4
u-boot/cmd/regulator.c
View File

@ -249,8 +249,8 @@ static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* Show all of them in a list, probing them as needed */
printf("%-20s %-10s %10s %10s %-10s\n", "Name", "Enabled", "uV", "mA",
"Mode");
for (ret = uclass_first_device(UCLASS_REGULATOR, &dev); dev;
ret = uclass_next_device(&dev))
for (uclass_first_device(UCLASS_REGULATOR, &dev); dev;
uclass_next_device(&dev))
do_status_line(dev);
return CMD_RET_SUCCESS;

88
u-boot/cmd/rockusb.c
View File

@ -151,6 +151,34 @@ cleanup:
return ret;
}
void rkusb_force_to_usb2(bool enable)
{
if (g_rkusb)
g_rkusb->force_usb2 = enable;
}
bool rkusb_force_usb2_enabled(void)
{
if (!g_rkusb)
return true;
return g_rkusb->force_usb2;
}
void rkusb_switch_to_usb3_enable(bool enable)
{
if (g_rkusb)
g_rkusb->switch_usb3 = enable;
}
bool rkusb_switch_usb3_enabled(void)
{
if (!g_rkusb)
return false;
return g_rkusb->switch_usb3;
}
static int do_rkusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
const char *usb_controller;
@ -164,6 +192,7 @@ static int do_rkusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
if (argc != 4)
return CMD_RET_USAGE;
re_enumerate:
usb_controller = argv[1];
devtype = argv[2];
devnum = argv[3];
@ -171,7 +200,7 @@ static int do_rkusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1")) {
pr_err("Forbid to flash mmc 1(sdcard)\n");
return CMD_RET_FAILURE;
} else if (!strcmp(devtype, "nvme") && !strcmp(devnum, "0")) {
} else if ((!strcmp(devtype, "nvme") || !strcmp(devtype, "scsi")) && !strcmp(devnum, "0")) {
/*
* Add partnum ":0" to active 'allow_whole_dev' partition
* search mechanism on multi storage, where there maybe not
@ -212,23 +241,34 @@ static int do_rkusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
goto cleanup_board;
}
s = env_get("serial#");
if (s) {
char *sn = (char *)calloc(strlen(s) + 1, sizeof(char));
char *sn_p = sn;
if (rkusb_switch_usb3_enabled()) {
/* Maskrom usb3 serialnumber get from upgrade tool */
rkusb_switch_to_usb3_enable(false);
} else {
s = env_get("serial#");
if (s) {
char *sn = (char *)calloc(strlen(s) + 1, sizeof(char));
char *sn_p = sn;
if (!sn)
goto cleanup_board;
if (!sn)
goto cleanup_board;
memcpy(sn, s, strlen(s));
while (*sn_p) {
if (*sn_p == '\\' || *sn_p == '/')
*sn_p = '_';
sn_p++;
memcpy(sn, s, strlen(s));
while (*sn_p) {
if (*sn_p == '\\' || *sn_p == '/')
*sn_p = '_';
sn_p++;
}
g_dnl_set_serialnumber(sn);
free(sn);
#if defined(CONFIG_SUPPORT_USBPLUG)
} else {
char sn[9] = "Rockchip";
g_dnl_set_serialnumber(sn);
#endif
}
g_dnl_set_serialnumber(sn);
free(sn);
}
rc = g_dnl_register("rkusb_ums_dnl");
@ -268,6 +308,16 @@ static int do_rkusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
rc = fsg_main_thread(NULL);
if (rc) {
if (rc == -ENODEV && rkusb_usb3_capable() &&
!rkusb_force_usb2_enabled()) {
printf("wait for usb3 connect timeout\n");
rkusb_force_to_usb2(true);
g_dnl_unregister();
usb_gadget_release(controller_index);
rkusb_fini();
goto re_enumerate;
}
/* Check I/O error */
if (rc == -EIO)
printf("\rCheck USB cable connection\n");
@ -279,6 +329,14 @@ static int do_rkusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
rc = CMD_RET_SUCCESS;
goto cleanup_register;
}
if (rkusb_switch_usb3_enabled()) {
printf("rockusb switch to usb3\n");
g_dnl_unregister();
usb_gadget_release(controller_index);
rkusb_fini();
goto re_enumerate;
}
}
cleanup_register:

14
u-boot/common/Kconfig
View File

@ -680,6 +680,20 @@ config HASH
and the algorithms it supports are defined in common/hash.c. See
also CMD_HASH for command-line access.
config BOARD_RNG_SEED
bool "Provide /chosen/rng-seed property to the linux kernel"
help
Selecting this option requires the board to define a
board_rng_seed() function, which should return a buffer
which will be used to populate the /chosen/rng-seed property
in the device tree for the OS being booted.
It is up to the board code (and more generally the whole
BSP) where and how to store (or generate) such a seed, how
to ensure a given seed is only used once, how to create a
new seed for use on subsequent boots, and whether or not the
kernel should account any entropy from the given seed.
endmenu
menu "MT support"

1
u-boot/common/Makefile
View File

@ -165,6 +165,7 @@ obj-$(CONFIG_IO_TRACE) += iotrace.o
obj-$(CONFIG_ANDROID_WRITE_KEYBOX) += write_keybox.o
obj-$(CONFIG_ANDROID_KEYMASTER_CA) += keymaster.o
obj-$(CONFIG_ANDROID_KEYMASTER_CA) += attestation_key.o
obj-$(CONFIG_ANDROID_KEYMASTER_CA) += id_attestation.o
endif
ifdef CONFIG_MP_BOOT

8
u-boot/common/board_info.c
View File

@ -5,8 +5,6 @@
#include <common.h>
#include <linux/libfdt.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/string.h>
int __weak checkboard(void)
{
@ -35,11 +33,5 @@ int __weak show_board_info(void)
printf("CPU: AArch32\n");
#endif
if (strstr(model, "rk3588") != NULL) {
printf("rpdzkj: pull down gpio0_b2 for init wifi\n");
writel(0xFFFF0400, 0xFD8A0008); // direction out
writel(0xFFFE0000, 0xFD8A0000); // output low
}
return checkboard();
}

14
u-boot/common/console.c
View File

@ -524,13 +524,6 @@ void putc(const char c)
putc_to_ram(c);
#endif
#ifdef CONFIG_DEBUG_UART
/* if we don't have a console yet, use the debug UART */
if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
printch(c);
return;
}
#endif
#ifdef CONFIG_CONSOLE_RECORD
if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start)
membuff_putbyte((struct membuff *)&gd->console_out, c);
@ -540,6 +533,13 @@ void putc(const char c)
return;
#endif
#ifdef CONFIG_DEBUG_UART
/* if we don't have a console yet, use the debug UART */
if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
printch(c);
return;
}
#endif
if (!gd->have_console)
return pre_console_putc(c);

4
u-boot/common/edid.c
View File

@ -2639,8 +2639,8 @@ static bool drm_valid_hdmi_vic(u8 vic)
return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
}
static void drm_add_hdmi_modes(struct hdmi_edid_data *data,
const struct drm_display_mode *mode)
void drm_add_hdmi_modes(struct hdmi_edid_data *data,
const struct drm_display_mode *mode)
{
struct drm_display_mode *mode_buf = data->mode_buf;

13
u-boot/common/fdt_support.c
View File

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <abuf.h>
#include <android_image.h>
#include <exports.h>
#include <fdt_support.h>
@ -354,6 +355,7 @@ __weak char *board_fdt_chosen_bootargs(void *fdt)
int fdt_chosen(void *fdt)
{
struct abuf buf = {};
int nodeoffset;
int err;
char *str; /* used to set string properties */
@ -369,6 +371,17 @@ int fdt_chosen(void *fdt)
if (nodeoffset < 0)
return nodeoffset;
if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
err = fdt_setprop(fdt, nodeoffset, "rng-seed",
abuf_data(&buf), abuf_size(&buf));
abuf_uninit(&buf);
if (err < 0) {
printf("WARNING: could not set rng-seed %s.\n",
fdt_strerror(err));
return err;
}
}
str = board_fdt_chosen_bootargs(fdt);
if (str) {
err = fdt_setprop(fdt, nodeoffset, "bootargs", str,

93
u-boot/common/id_attestation.c Normal file
View File

@ -0,0 +1,93 @@
/*
* Copyright 2023, Rockchip Electronics Co., Ltd
* callen, <callen.cai@rock-chips.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <keymaster.h>
#include "id_attestation.h"
#define ID_ATTESTATION_FILE "attestation_ids"
/* Maximum file name size.*/
#define STORAGE_ID_LENGTH_MAX 64
void printAttestationIds(const AttestationIds *ids)
{
printf("AttestationIds:\n");
printf(" brand: %s\n", ids->brand);
printf(" device: %s\n", ids->device);
printf(" product: %s\n", ids->product);
printf(" serial: %s\n", ids->serial);
printf(" imei: %s\n", ids->imei);
printf(" second_imei: %s\n", ids->second_imei);
printf(" meid: %s\n", ids->meid);
printf(" manufacturer: %s\n", ids->manufacturer);
printf(" model: %s\n", ids->model);
}
uint32_t write_to_keymaster(u8 *filename, uint32_t filename_size,
u8 *data, uint32_t data_size);
/* read id attestation digest len */
uint32_t read_id_attestation_digest(const char *ids_digest_file, uint32_t *ids_digest_len)
{
int len = sizeof(AttestationIds);
u8 ids_digest[len];
TEEC_Result ret = read_from_keymaster((u8 *)ids_digest_file, strlen(ids_digest_file),
(u8 *)ids_digest, len);
if (ret != TEEC_SUCCESS)
*ids_digest_len = 0;
else
*ids_digest_len = len;
MSG("%s file:%s ,digest_len=%d,ret=%x\n", __func__, ids_digest_file, *ids_digest_len, ret);
return ret;
}
uint32_t write_id_attestation(const char *ids_file, AttestationIds *ids, uint32_t ids_len)
{
TEEC_Result ret = write_to_keymaster((u8 *)ids_file, strlen(ids_file),
(u8 *)ids, ids_len);
MSG("%s ids_file=%s ret=%0x\n", __func__, ids_file, ret);
return ret;
}
atap_result write_id_attestation_to_secure_storage(u8* received_data, uint32_t len)
{
AttestationIds ids;
u32 ids_len;
AttestationIds ids_read;
char ids_file[STORAGE_ID_LENGTH_MAX] = { 0 };
ids_len = (received_data[5] << 8) | received_data[4];
printf("%s size=%d\n", __func__, ids_len);
if (ids_len != sizeof(AttestationIds)) {
printf("%s AttestationIds size is %zu)\n", __func__, sizeof(AttestationIds));
return ATAP_RESULT_ERROR_INVALID_HEAD;
}
memcpy(&ids, received_data + 8, len);
#if DEBUG
printAttestationIds(&ids);
#endif
/* now you have got the whole AttestationIds data....*/
memcpy(ids_file, ID_ATTESTATION_FILE, sizeof(ID_ATTESTATION_FILE));
TEEC_Result ret = read_from_keymaster((u8 *)ids_file,
strlen(ids_file),
(u8*)&ids_read,
sizeof(AttestationIds));
MSG("read id attestation ret=%0x\n", ret);
if (ret == TEEC_SUCCESS) {
printf("id attestation already exsit,you cannot update it!");
#if DEBUG
printAttestationIds(&ids_read);
#endif
ret = ATAP_RESULT_ERROR_ALREADY_EXSIT;
return ret;
}
ret = write_id_attestation(ids_file, &ids, ids_len);
printf("write id attestation : ret=%d\n", ret);
return ret;
}

31
u-boot/common/image-android.c
View File

@ -1090,7 +1090,16 @@ extract_boot_image_v34_header(struct blk_desc *dev_desc,
return NULL;
}
/* Start from android-13 GKI, it doesn't assign 'os_version' */
/*
* [Start from android-13 GKI, it doesn't assign 'os_version']
*
* Android_12 or later are header_version >= 4.
* Android_13(GKI) introduce a new partition named "init_boot" and
* doesn't assign 'os_version' any more(ie. default 0).
*
* We only assign 'os_version' depend on whether there is
* init_boot partition or not.
*/
if (boot_hdr->header_version >= 4 && boot_hdr->os_version == 0) {
if (part_get_info_by_name(dev_desc,
ANDROID_PARTITION_INIT_BOOT, &part) > 0)
@ -1171,7 +1180,25 @@ int populate_boot_info(const struct boot_img_hdr_v34 *boot_hdr,
/* fixed in v3 */
hdr->page_size = 4096;
hdr->header_version = boot_hdr->header_version;
hdr->os_version = boot_hdr->os_version;
/*
* [Start from android-13 GKI, it doesn't assign 'os_version']
*
* Android_12 or later are header_version >= 4.
* Android_13(GKI) introduce a new partition named "init_boot" and
* doesn't assign 'os_version' any more(ie. default 0).
*
* We only assign 'os_version' depend on whether there is
* init_boot partition or not.
*/
if (boot_hdr->header_version >= 4 && boot_hdr->os_version == 0) {
if (init_boot_hdr)
hdr->os_version = 13 << 25;
if (!hdr->os_version)
printf("WARN: it seems to be an invalid Android os_version: 0\n");
} else {
hdr->os_version = boot_hdr->os_version;
}
memset(hdr->name, 0, ANDR_BOOT_NAME_SIZE);
strncpy(hdr->name, (const char *)vendor_boot_hdr->name, ANDR_BOOT_NAME_SIZE);

2
u-boot/common/image-sig.c
View File

@ -439,7 +439,7 @@ int fit_config_check_sig(const void *fit, int noffset, int required_keynode,
#if !defined(USE_HOSTCC)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FIT_HW_CRYPTO) && \
defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
rsa_burn_key_hash(&info);
return rsa_burn_key_hash(&info);
#endif
#endif

4
u-boot/common/spl/Kconfig
View File

@ -884,7 +884,9 @@ config SPL_OPTEE
config SPL_AB
bool "Support AB system boot"
depends on SPL && SPL_EFI_PARTITION
depends on SPL && SPL_LIBDISK_SUPPORT
select SPL_MTD_WRITE if SPL_MTD_SUPPORT
select SPL_MMC_WRITE if SPL_MMC_SUPPORT
help
Enable this config to support AB system boot.

8
u-boot/common/spl/Makefile
View File

@ -25,10 +25,10 @@ endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
ifdef CONFIG_SPL_KERNEL_BOOT_PREBUILT
ifdef CONFIG_ARM64
obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit_tb_arm64.o
else
obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit_tb_arm32.o
ifeq ($(CONFIG_$(SPL_TPL_)LOAD_FIT),y)
obj-$(CONFIG_ARM64) += spl_fit_tb_arm64.o
obj-$(CONFIG_ROCKCHIP_RV1106) += spl_fit_tb_rv1106.o
obj-$(CONFIG_ROCKCHIP_RV1126) += spl_fit_tb_rv1126.o
endif
else
obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o

5
u-boot/common/spl/spl.c
View File

@ -661,8 +661,13 @@ void preloader_console_init(void)
gd->have_console = 1;
#ifdef BUILD_SPL_TAG
puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
U_BOOT_TIME "), fwver: "BUILD_SPL_TAG"\n");
#else
puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
U_BOOT_TIME ")\n");
#endif
#ifdef CONFIG_SPL_DISPLAY_PRINT
spl_display_print();
#endif

36
u-boot/common/spl/spl_ab.c
View File

@ -284,6 +284,35 @@ static int spl_save_metadata_if_changed(struct blk_desc *dev_desc,
return 0;
}
static void spl_slot_set_unbootable(AvbABSlotData* slot)
{
slot->priority = 0;
slot->tries_remaining = 0;
slot->successful_boot = 0;
}
/* Ensure all unbootable and/or illegal states are marked as the
* canonical 'unbootable' state, e.g. priority=0, tries_remaining=0,
* and successful_boot=0.
*/
static void spl_slot_normalize(AvbABSlotData* slot)
{
if (slot->priority > 0) {
if (slot->tries_remaining == 0 && !slot->successful_boot) {
/* We've exhausted all tries -> unbootable. */
spl_slot_set_unbootable(slot);
}
if (slot->tries_remaining > 0 && slot->successful_boot) {
/* Illegal state - avb_ab_mark_slot_successful() and so on
* will clear tries_remaining when setting successful_boot.
*/
spl_slot_set_unbootable(slot);
}
} else {
spl_slot_set_unbootable(slot);
}
}
/* If verify fail in a/b system, then decrease 1. */
int spl_ab_decrease_tries(struct blk_desc *dev_desc)
{
@ -309,6 +338,13 @@ int spl_ab_decrease_tries(struct blk_desc *dev_desc)
memcpy(&ab_data_orig, &ab_data, sizeof(AvbABData));
/* Ensure data is normalized, e.g. illegal states will be marked as
* unbootable and all unbootable states are represented with
* (priority=0, tries_remaining=0, successful_boot=0).
*/
spl_slot_normalize(&ab_data.slots[0]);
spl_slot_normalize(&ab_data.slots[1]);
/* ... and decrement tries remaining, if applicable. */
if (!ab_data.slots[slot_index].successful_boot &&
ab_data.slots[slot_index].tries_remaining > 0)

12882
u-boot/common/spl/spl_fit_tb_rv1106.S Normal file
View File

File diff suppressed because it is too large Load Diff

0
u-boot/common/spl/spl_fit_tb_arm32.S → u-boot/common/spl/spl_fit_tb_rv1126.S
View File

9
u-boot/common/stdio.c
View File

@ -368,16 +368,11 @@ int stdio_add_devices(void)
*/
#ifndef CONFIG_SYS_CONSOLE_IS_IN_ENV
struct udevice *vdev;
# ifndef CONFIG_DM_KEYBOARD
int ret;
# endif
for (ret = uclass_first_device(UCLASS_VIDEO, &vdev);
for (uclass_first_device(UCLASS_VIDEO, &vdev);
vdev;
ret = uclass_next_device(&vdev))
uclass_next_device(&vdev))
;
if (ret)
printf("%s: Video device failed (ret=%d)\n", __func__, ret);
#endif /* !CONFIG_SYS_CONSOLE_IS_IN_ENV */
#else
# if defined(CONFIG_LCD)

15
u-boot/common/write_keybox.c Executable file → Normal file
View File

@ -7,6 +7,7 @@
#include <boot_rkimg.h>
#include <stdlib.h>
#include <attestation_key.h>
#include <id_attestation.h>
#include <write_keybox.h>
#include <keymaster.h>
#include <optee_include/OpteeClientApiLib.h>
@ -18,6 +19,7 @@
#define BOOT_FROM_EMMC (1 << 1)
#define WIDEVINE_TAG "KBOX"
#define ATTESTATION_TAG "ATTE"
#define ID_ATTESTATION_TAG "IDAT"
#define PLAYREADY30_TAG "SL30"
TEEC_Result write_to_security_storage(uint8_t is_use_rpmb,
@ -224,6 +226,7 @@ uint32_t write_keybox_to_secure_storage(uint8_t *received_data, uint32_t len)
{
uint8_t *widevine_data;
uint8_t *attestation_data;
uint8_t *id_attestation_data;
uint8_t *playready_sl30_data;
uint32_t key_size;
uint32_t data_size;
@ -255,6 +258,8 @@ uint32_t write_keybox_to_secure_storage(uint8_t *received_data, uint32_t len)
WIDEVINE_TAG, len);
attestation_data = (uint8_t *)new_strstr((char *)received_data,
ATTESTATION_TAG, len);
id_attestation_data = (uint8_t *)new_strstr((char *)received_data,
ID_ATTESTATION_TAG, len);
playready_sl30_data = (uint8_t *)new_strstr((char *)received_data,
PLAYREADY30_TAG, len);
if (widevine_data) {
@ -293,6 +298,16 @@ uint32_t write_keybox_to_secure_storage(uint8_t *received_data, uint32_t len)
rc = -EIO;
printf("write attestation key to secure storage fail\n");
}
} else if (id_attestation_data) {
/* id attestation */
ret = write_id_attestation_to_secure_storage(id_attestation_data, len);
if (ret == ATAP_RESULT_OK) {
rc = 0;
printf("write id attestation success!\n");
} else {
rc = -EIO;
printf("write id attestation failed\n");
}
} else if (playready_sl30_data) {
/* PlayReady SL3000 root key */
uint32_t ret;

1
u-boot/configs/gki.config Normal file
View File

@ -0,0 +1 @@
CONFIG_ANDROID_AB=y

1
u-boot/configs/rk-amp.config
View File

@ -1,3 +1,2 @@
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_AMP=y
CONFIG_ROCKCHIP_AMP=y

2
u-boot/configs/rk322x_defconfig
View File

@ -86,6 +86,8 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_IO_DOMAIN=y
CONFIG_ROCKCHIP_IO_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y

14
u-boot/configs/rk3308-ia.config Normal file
View File

@ -0,0 +1,14 @@
# CONFIG_CMD_ATAGS is not set
# CONFIG_CMD_DHCP is not set
# CONFIG_CMD_MMC is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_PING is not set
# CONFIG_DM_ETH is not set
# CONFIG_DM_MMC is not set
# CONFIG_FIT is not set
# CONFIG_LED is not set
# CONFIG_MMC is not set
# CONFIG_NET is not set
# CONFIG_PHYLIB is not set
# CONFIG_REGEX is not set
# CONFIG_RKNANDC_NAND is not set

2
u-boot/configs/rk3308_defconfig
View File

@ -81,6 +81,8 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_RK816=y
CONFIG_IO_DOMAIN=y
CONFIG_ROCKCHIP_IO_DOMAIN=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y

8
u-boot/configs/rk3328_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_ROCKCHIP_RK3328=y
CONFIG_RKIMG_BOOTLOADER=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
@ -89,6 +88,8 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PINCTRL=y
CONFIG_IO_DOMAIN=y
CONFIG_ROCKCHIP_IO_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
@ -118,11 +119,11 @@ CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
@ -133,7 +134,6 @@ CONFIG_DRM_ROCKCHIP_TVE=y
CONFIG_LCD=y
# CONFIG_IRQ is not set
CONFIG_USE_TINY_PRINTF=y
CONFIG_PANIC_HANG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

25
u-boot/configs/rk3528-usbplug.config Normal file
View File

@ -0,0 +1,25 @@
CONFIG_BASE_DEFCONFIG="rockchip-usbplug_defconfig"
# CONFIG_TARGET_EVB_RV1126 is not set
# CONFIG_ROCKCHIP_RV1126 is not set
CONFIG_DEBUG_UART_BASE=0xff9f0000
CONFIG_DEFAULT_DEVICE_TREE="rk3528-evb"
CONFIG_ROCKCHIP_RK3528=y
CONFIG_TARGET_EVB_RK3528=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ROCKCHIP_NEW_IDB=y
# CONFIG_CLK_SCMI is not set
# CONFIG_SCMI_FIRMWARE is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_DW_ROCKCHIP is not set
CONFIG_ROCKCHIP_BOOT_MODE_REG=0xff370200
CONFIG_ROCKCHIP_STIMER_BASE=0xff620000
CONFIG_ROCKCHIP_IRAM_START_ADDR=0xfe480000
# CONFIG_ROCKCHIP_SFC is not set
# CONFIG_MTD is not set
# CONFIG_MTD_BLK is not set
# CONFIG_MTD_DEVICE is not set
# CONFIG_SPI_FLASH is not set
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_DM_RESET=y

25
u-boot/configs/rk3562-usbplug.config Normal file
View File

@ -0,0 +1,25 @@
CONFIG_BASE_DEFCONFIG="rockchip-usbplug_defconfig"
# CONFIG_TARGET_EVB_RV1126 is not set
# CONFIG_ROCKCHIP_RV1126 is not set
CONFIG_DEBUG_UART_BASE=0xff210000
CONFIG_DEFAULT_DEVICE_TREE="rk3562-evb"
CONFIG_ROCKCHIP_RK3562=y
CONFIG_TARGET_EVB_RK3562=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ROCKCHIP_NEW_IDB=y
# CONFIG_CLK_SCMI is not set
# CONFIG_SCMI_FIRMWARE is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_DW_ROCKCHIP is not set
CONFIG_ROCKCHIP_BOOT_MODE_REG=0xff010220
CONFIG_ROCKCHIP_STIMER_BASE=0xffa90020
CONFIG_ROCKCHIP_IRAM_START_ADDR=0xfe480000
# CONFIG_ROCKCHIP_SFC is not set
# CONFIG_MTD is not set
# CONFIG_MTD_BLK is not set
# CONFIG_MTD_DEVICE is not set
# CONFIG_SPI_FLASH is not set
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_DM_RESET=y

1
u-boot/configs/rk3562_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set

226
u-boot/configs/rk3568-pcie-ep_defconfig Normal file
View File

@ -0,0 +1,226 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_HW_CRYPTO=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_SHA256_SUPPORT=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_PCIE_EP_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SPL_AB=y
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_BOOT_ANDROID=y
CONFIG_CMD_BOOT_ROCKCHIP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
# CONFIG_CMD_MISC is not set
# CONFIG_CMD_CHARGE_DISPLAY is not set
CONFIG_CMD_MTD_BLK=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_NET_TFTP_VARS is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_SCMI=y
CONFIG_DM_CRYPTO=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_ROCKCHIP_CRYPTO_V2=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_SCMI_FIRMWARE=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEY=y
CONFIG_RK8XX_PWRKEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_SPI_NAND=y
# CONFIG_SPI_NAND_TOSHIBA is not set
# CONFIG_SPI_NAND_BIWIN is not set
# CONFIG_SPI_NAND_ETRON is not set
# CONFIG_SPI_NAND_JSC is not set
# CONFIG_SPI_NAND_SILICONGO is not set
# CONFIG_SPI_NAND_UNIM is not set
# CONFIG_SPI_NAND_SKYHIGH is not set
# CONFIG_SPI_NAND_GSTO is not set
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_RK817=y
CONFIG_IO_DOMAIN=y
CONFIG_ROCKCHIP_IO_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RAMDISK=y
CONFIG_RAMDISK_RO=y
CONFIG_DM_DMC=y
CONFIG_ROCKCHIP_DMC_FSP=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_DW_HDMI=y
CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y
CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
CONFIG_DRM_ROCKCHIP_LVDS=y
CONFIG_DRM_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=9
CONFIG_LCD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_N_SIZE=0x200
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_XBC=y
CONFIG_SHA512=y
CONFIG_LZ4=y
CONFIG_LZMA=y
CONFIG_SPL_GZIP=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_AVB_LIBAVB=y
CONFIG_AVB_LIBAVB_AB=y
CONFIG_AVB_LIBAVB_ATX=y
CONFIG_AVB_LIBAVB_USER=y
CONFIG_RK_AVB_LIBAVB_USER=y
CONFIG_OPTEE_CLIENT=y
CONFIG_OPTEE_V2=y
CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y

14
u-boot/configs/rk3568-usbplug.config
View File

@ -9,3 +9,17 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ROCKCHIP_NEW_IDB=y
# CONFIG_CLK_SCMI is not set
# CONFIG_SCMI_FIRMWARE is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_DW_ROCKCHIP is not set
CONFIG_ROCKCHIP_BOOT_MODE_REG=0xfdc20200
CONFIG_ROCKCHIP_STIMER_BASE=0xfdd1c020
CONFIG_ROCKCHIP_IRAM_START_ADDR=0xfdcc0000
# CONFIG_ROCKCHIP_SFC is not set
# CONFIG_MTD is not set
# CONFIG_MTD_BLK is not set
# CONFIG_MTD_DEVICE is not set
# CONFIG_SPI_FLASH is not set
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_DM_RESET=y

4
u-boot/configs/rk3568_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_DEBUG_UART=y
CONFIG_IMAGE_GZIP=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_HW_CRYPTO=y
@ -33,6 +34,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
@ -166,7 +168,7 @@ CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=115200
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2

2
u-boot/configs/rk3583.config Normal file
View File

@ -0,0 +1,2 @@
CONFIG_BASE_DEFCONFIG="rk3588_defconfig"
CONFIG_LOADER_INI="RK3583MINIALL.ini"

18
u-boot/configs/rk3588-ab-car.config Normal file
View File

@ -0,0 +1,18 @@
CONFIG_ANDROID_AB=y
CONFIG_BASE_DEFCONFIG="rk3588_defconfig"
# CONFIG_CMD_ANDROID_AB_SELECT is not set
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96789=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO_NCA9539=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX111=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX121=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM=y
CONFIG_SERDES_DISPLAY=y

2
u-boot/configs/rk3588-qnx_defconfig
View File

@ -139,7 +139,7 @@ CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK860X=y
CONFIG_REGULATOR_RK806=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_CHARGER_BQ25700=y
CONFIG_CHARGER_BQ25890=y
CONFIG_CHARGER_SC8551=y

26
u-boot/configs/rk3588-usbplug.config Normal file
View File

@ -0,0 +1,26 @@
CONFIG_BASE_DEFCONFIG="rockchip-usbplug_defconfig"
# CONFIG_TARGET_EVB_RV1126 is not set
# CONFIG_ROCKCHIP_RV1126 is not set
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_TARGET_EVB_RK3588=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ROCKCHIP_NEW_IDB=y
# CONFIG_CLK_SCMI is not set
# CONFIG_SCMI_FIRMWARE is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_DW_ROCKCHIP is not set
CONFIG_ROCKCHIP_BOOT_MODE_REG=0xfd588080
CONFIG_ROCKCHIP_STIMER_BASE=0xfd8c8000
CONFIG_ROCKCHIP_IRAM_START_ADDR=0xff000000
# CONFIG_ROCKCHIP_SFC is not set
# CONFIG_MTD is not set
# CONFIG_MTD_BLK is not set
# CONFIG_MTD_DEVICE is not set
# CONFIG_SPI_FLASH is not set
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_DM_RESET=y
CONFIG_OF_LIVE=y

16
u-boot/configs/rk3588_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_PSTORE=y
CONFIG_ROCKCHIP_MINIDUMP=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RK3588=y
@ -21,6 +22,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb"
CONFIG_DEBUG_UART=y
CONFIG_IMAGE_GZIP=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_HW_CRYPTO=y
@ -34,13 +36,14 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
CONFIG_SPL_MMC_WRITE=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_SPL_AB=y
@ -58,6 +61,7 @@ CONFIG_CMD_DTIMG=y
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
@ -104,6 +108,7 @@ CONFIG_SPL_SCMI_FIRMWARE=y
CONFIG_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_NCA9539_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEY=y
@ -160,7 +165,7 @@ CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK860X=y
CONFIG_REGULATOR_RK806=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_CHARGER_BQ25700=y
CONFIG_CHARGER_BQ25890=y
CONFIG_CHARGER_SC8551=y
@ -176,7 +181,7 @@ CONFIG_RAMDISK_RO=y
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=115200
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
@ -202,11 +207,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_MAXIM_MAX96745=y
CONFIG_DRM_MAXIM_MAX96755F=y
CONFIG_DRM_PANEL_ROHM_BU18RL82=y
CONFIG_DRM_PANEL_MAXIM_MAX96752F=y
CONFIG_DRM_ROHM_BU18XL82=y
CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
CONFIG_DRM_ROCKCHIP_DW_DP=y

121
u-boot/configs/rv1106-spi-nand-tb-nofastae_defconfig Normal file
View File

@ -0,0 +1,121 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RV1106=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
# CONFIG_ROCKCHIP_SET_SN is not set
# CONFIG_ROCKCHIP_SET_ETHADDR is not set
CONFIG_LOADER_INI="RV1106MINIALL_SPI_NOR_TB_NOMCU.ini"
CONFIG_TRUST_INI="RV1106TOS_TB.ini"
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RV1106=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rv1106-evb"
CONFIG_DEBUG_UART=y
# CONFIG_DISTRO_DEFAULTS is not set
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_SPL_FIT_IMAGE_KB=512
CONFIG_SPL_FIT_IMAGE_MULTIPLE=1
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_SKIP_RELOCATE_UBOOT is not set
CONFIG_SPL_ADC_SUPPORT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_KERNEL_BOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_MTD_BLK=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_U_BOOT_REMOVE_PROPS="interrupt-parent"
CONFIG_ENVF=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_SPL_BLK_READ_PREPARE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_ROCKCHIP_GPIO=y
# CONFIG_DM_I2C is not set
CONFIG_SPL_INPUT=y
CONFIG_DM_KEY=y
CONFIG_ADC_KEY=y
CONFIG_SPL_ADC_KEY=y
CONFIG_SPL_MISC=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
# CONFIG_MMC is not set
# CONFIG_DM_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
# CONFIG_DM_REGULATOR is not set
# CONFIG_DM_PWM is not set
CONFIG_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xff4c0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
# CONFIG_SYSRESET_SYSCON_REBOOT is not set
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

122
u-boot/configs/rv1106-spi-nand-tb_defconfig Normal file
View File

@ -0,0 +1,122 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RV1106=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_META=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
# CONFIG_ROCKCHIP_SET_SN is not set
# CONFIG_ROCKCHIP_SET_ETHADDR is not set
CONFIG_LOADER_INI="RV1106MINIALL_SPI_NAND_TB.ini"
CONFIG_TRUST_INI="RV1106TOS_TB.ini"
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RV1106=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rv1106-evb"
CONFIG_DEBUG_UART=y
# CONFIG_DISTRO_DEFAULTS is not set
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_SPL_FIT_IMAGE_KB=512
CONFIG_SPL_FIT_IMAGE_MULTIPLE=1
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_SKIP_RELOCATE_UBOOT is not set
CONFIG_SPL_ADC_SUPPORT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_KERNEL_BOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_MTD_BLK=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_U_BOOT_REMOVE_PROPS="interrupt-parent"
CONFIG_ENVF=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_SPL_BLK_READ_PREPARE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_ROCKCHIP_GPIO=y
# CONFIG_DM_I2C is not set
CONFIG_SPL_INPUT=y
CONFIG_DM_KEY=y
CONFIG_ADC_KEY=y
CONFIG_SPL_ADC_KEY=y
CONFIG_SPL_MISC=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
# CONFIG_MMC is not set
# CONFIG_DM_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
# CONFIG_DM_REGULATOR is not set
# CONFIG_DM_PWM is not set
CONFIG_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xff4c0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
# CONFIG_SYSRESET_SYSCON_REBOOT is not set
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

48
u-boot/configs/rv1106-usbplug.config Executable file
View File

@ -0,0 +1,48 @@
CONFIG_BASE_DEFCONFIG="rockchip-usbplug_defconfig"
CONFIG_BAUDRATE=115200
CONFIG_CMD_PINMUX=y
# CONFIG_CMD_REGULATOR is not set
CONFIG_CMD_USB=y
CONFIG_DEBUG_UART_BASE=0xff4c0000
CONFIG_DEFAULT_DEVICE_TREE="rv1106-evb"
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR=y
# CONFIG_NOP_PHY is not set
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY=y
# CONFIG_PINCONF is not set
CONFIG_PINCONF_RECURSIVE=y
# CONFIG_PINCTRL_AT91 is not set
# CONFIG_PINCTRL_AT91PIO4 is not set
CONFIG_PINCTRL_FULL=y
CONFIG_PINCTRL_GENERIC=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_STM32 is not set
CONFIG_PINCTRL=y
CONFIG_PINMUX=y
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_PWM is not set
# CONFIG_REGULATOR_RK860X is not set
CONFIG_ROCKCHIP_BOOT_MODE_REG=0xff020200
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_IRAM_START_ADDR=0xff6c0000
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_ROCKCHIP_RV1106=y
# CONFIG_ROCKCHIP_RV1126 is not set
CONFIG_ROCKCHIP_STIMER_BASE=0xff590020
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
# CONFIG_SPL_DM_REGULATOR_FIXED is not set
# CONFIG_SPL_DM_REGULATOR is not set
CONFIG_SYS_BOARD="evb_rv1106"
CONFIG_SYS_CONFIG_NAME="evb_rv1106"
CONFIG_TARGET_EVB_RV1106=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x110c
CONFIG_USB_HOST=y
CONFIG_USB_STORAGE=y
# CONFIG_USB_XHCI_DWC3 is not set
# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_PCI is not set

9
u-boot/configs/rv1106_defconfig
View File

@ -42,6 +42,7 @@ CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_MMC_WRITE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_AB=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
@ -108,14 +109,6 @@ CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x3
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_RK630=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y

35
u-boot/configs/rv1126-emmc-tb-nofastae.config Normal file
View File

@ -0,0 +1,35 @@
CONFIG_BASE_DEFCONFIG="rv1126_defconfig"
# CONFIG_CMD_MTD_BLK is not set
# CONFIG_CMD_NAND is not set
# CONFIG_CMD_SF is not set
# CONFIG_CMD_SPI is not set
CONFIG_LOADER_INI="RV1126MINIALL_EMMC_TB.ini"
CONFIG_MMC_USE_PRE_CONFIG=y
# CONFIG_MTD_DEVICE is not set
# CONFIG_MTD is not set
# CONFIG_MTD_NAND_BBT_USING_FLASH is not set
# CONFIG_NAND is not set
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_ROCKCHIP_SFC is not set
# CONFIG_SPI_FLASH is not set
# CONFIG_SPI_MEM is not set
# CONFIG_SPL_AB is not set
CONFIG_SPL_ADC_KEY=y
CONFIG_SPL_ADC_SUPPORT=y
CONFIG_SPL_BLK_READ_PREPARE=y
# CONFIG_SPL_CROS_EC_KEYB is not set
CONFIG_SPL_DM_FUEL_GAUGE=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_INPUT=y
CONFIG_SPL_KERNEL_BOOT=y
# CONFIG_SPL_MTD_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
# CONFIG_SPL_PINCTRL is not set
# CONFIG_SPL_POWER_FG_CW201X is not set
CONFIG_SPL_POWER_FG_RK817=y
# CONFIG_SPL_POWER_FG_RK818 is not set
CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD=3400
# CONFIG_SPL_SPI_FLASH_SUPPORT is not set
# CONFIG_SPL_SPI_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_TRUST_INI="RV1126TOS_TB_NOMCU.ini"

184
u-boot/configs/rv1126-spl-slc-nand_defconfig Normal file
View File

@ -0,0 +1,184 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RV1126=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_UIMAGE=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_UART_MUX_SEL_M=2
CONFIG_ROCKCHIP_SFC_IOMUX=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RV1126=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rv1126-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_HW_CRYPTO=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_BOOTDELAY=0
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
# CONFIG_ANDROID_WRITE_KEYBOX is not set
# CONFIG_ANDROID_KEYMASTER_CA is not set
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_SHA256_SUPPORT=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MTD_WRITE=y
CONFIG_SPL_OPTEE=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_BOOT_ANDROID=y
CONFIG_CMD_BOOT_ROCKCHIP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
# CONFIG_CMD_CHARGE_DISPLAY is not set
CONFIG_CMD_MTD_BLK=y
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_U_BOOT_REMOVE_PROPS="interrupt-parent"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_CRYPTO=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_ROCKCHIP_CRYPTO_V2=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEY=y
CONFIG_RK8XX_PWRKEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_MISC_DECOMPRESS=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_NAND_BBT_USING_FLASH=y
CONFIG_NAND=y
CONFIG_NAND_ROCKCHIP=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x4000
CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x10000
CONFIG_SF_DEFAULT_MODE=0x1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_NANENG_USB2=y
CONFIG_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_RK817=y
CONFIG_IO_DOMAIN=y
CONFIG_ROCKCHIP_IO_DOMAIN=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xff570000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPI_MEM=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x110b
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_DRM_ROCKCHIP_RGB=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_N_SIZE=0x100
CONFIG_RSA_E_SIZE=0x100
CONFIG_RSA_C_SIZE=0x14
CONFIG_SHA512=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_OPTEE_CLIENT=y
CONFIG_OPTEE_V2=y

4
u-boot/disk/part_env.c
View File

@ -157,7 +157,7 @@ static int part_get_info_env(struct blk_desc *dev_desc, int idx,
{
struct env_part *p = NULL;
struct list_head *node;
int part_num = 1;
int part_num = 0;
int ret = 0;
if (idx < 1) {
@ -175,9 +175,9 @@ static int part_get_info_env(struct blk_desc *dev_desc, int idx,
list_for_each(node, &parts_head) {
p = list_entry(node, struct env_part, node);
part_num++;
if (idx == part_num)
break;
part_num++;
}
if (part_num < idx) {

4
u-boot/disk/part_rkparm.c
View File

@ -176,7 +176,7 @@ static int part_get_info_rkparm(struct blk_desc *dev_desc, int idx,
{
struct list_head *node;
struct rkparm_part *p = NULL;
int part_num = 1;
int part_num = 0;
int ret = 0;
if (idx < 1) {
@ -195,9 +195,9 @@ static int part_get_info_rkparm(struct blk_desc *dev_desc, int idx,
list_for_each(node, &parts_head) {
p = list_entry(node, struct rkparm_part, node);
part_num ++;
if (idx == part_num)
break;
part_num ++;
}
if (part_num < idx) {

4
u-boot/disk/part_rkram.c
View File

@ -99,7 +99,7 @@ static int part_get_info_rkram_part(struct blk_desc *dev_desc, int idx,
{
struct rkram_part *p = NULL;
struct list_head *node;
int part_num = 1;
int part_num = 0;
if (idx < 1) {
printf("Invalid partition no.%d\n", idx);
@ -111,9 +111,9 @@ static int part_get_info_rkram_part(struct blk_desc *dev_desc, int idx,
list_for_each(node, &parts_head) {
p = list_entry(node, struct rkram_part, node);
part_num++;
if (idx == part_num)
break;
part_num++;
}
if (part_num < idx) {

65
u-boot/doc/device-tree-bindings/pinctrl/pinctrl-bindings.txt
View File

@ -119,7 +119,8 @@ For example:
The contents of each of those pin configuration child nodes is defined
entirely by the binding for the individual pin controller device. There
exists no common standard for this content.
exists no common standard for this content. The pinctrl framework only
provides generic helper bindings that the pin controller driver can use.
The pin configuration nodes need not be direct children of the pin controller
device; they may be grandchildren, for example. Whether this is legal, and
@ -156,6 +157,29 @@ state_2_node_a {
pins = "mfio29", "mfio30";
};
For hardware where pin multiplexing configurations have to be specified for
each single pin the number of required sub-nodes containing "pin" and
"function" properties can quickly escalate and become hard to write and
maintain.
For cases like this, the pin controller driver may use the pinmux helper
property, where the pin identifier is provided with mux configuration settings
in a pinmux group. A pinmux group consists of the pin identifier and mux
settings represented as a single integer or an array of integers.
The pinmux property accepts an array of pinmux groups, each of them describing
a single pin multiplexing configuration.
pincontroller {
state_0_node_a {
pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
};
};
Each individual pin controller driver bindings documentation shall specify
how pin IDs and pin multiplexing configuration are defined and assembled
together in a pinmux group.
== Generic pin configuration node content ==
Many data items that are represented in a pin configuration node are common
@ -168,12 +192,15 @@ structure of the DT nodes that contain these properties.
Supported generic properties are:
pins - the list of pins that properties in the node
apply to (either this or "group" has to be
apply to (either this, "group" or "pinmux" has to be
specified)
group - the group to apply the properties to, if the driver
supports configuration of whole groups rather than
individual pins (either this or "pins" has to be
specified)
individual pins (either this, "pins" or "pinmux" has
to be specified)
pinmux - the list of numeric pin ids and their mux settings
that properties in the node apply to (either this,
"pins" or "groups" have to be specified)
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
@ -184,17 +211,30 @@ drive-push-pull - drive actively high and low
drive-open-drain - drive with open drain
drive-open-source - drive with open source
drive-strength - sink or source at most X mA
input-enable - enable input on pin (no effect on output)
input-disable - disable input on pin (no effect on output)
drive-strength-microamp - sink or source at most X uA
input-enable - enable input on pin (no effect on output, such as
enabling an input buffer)
input-disable - disable input on pin (no effect on output, such as
disabling an input buffer)
input-schmitt-enable - enable schmitt-trigger mode
input-schmitt-disable - disable schmitt-trigger mode
input-debounce - debounce mode with debound time X
power-source - select between different power supplies
low-power-enable - enable low power mode
low-power-disable - disable low power mode
output-disable - disable output on a pin (such as disable an output
buffer)
output-enable - enable output on a pin without actively driving it
(such as enabling an output buffer)
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
sleep-hardware-state - indicate this is sleep related state which will be programmed
into the registers for the sleep state.
slew-rate - set the slew rate
skew-delay - this affects the expected clock skew on input pins
and the delay before latching a value to an output
pin. Typically indicates how many double-inverters are
used to delay the signal.
For example:
@ -216,6 +256,12 @@ state_2_node_a {
bias-pull-up;
};
};
state_3_node_a {
mux {
pinmux = <GPIOx_PINm_MUXn>, <GPIOx_PINj_MUXk)>;
input-enable;
};
};
Some of the generic properties take arguments. For those that do, the
arguments are described below.
@ -224,11 +270,18 @@ arguments are described below.
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- pinmux takes a list of pin IDs and mux settings as required argument. The
specific bindings for the hardware defines:
- How pin IDs and mux settings are defined and assembled together in a single
integer or an array of integers.
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
- drive-strength takes as argument the target strength in mA.
- drive-strength-microamp takes as argument the target strength in uA.
- input-debounce takes the debounce time in usec as argument
or 0 to disable debouncing

16
u-boot/drivers/ata/ahci.c
View File

@ -115,6 +115,22 @@ int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
int j = 0;
void __iomem *port_mmio = uc_priv->port[port].port_mmio;
/*
* Add port reset before link up to fix some device link up
* fail.
*/
writel(0x4, port_mmio + PORT_SCR_CTL);
udelay(10000);
writel(0x1, port_mmio + PORT_SCR_CTL);
udelay(10000);
writel(0x0, port_mmio + PORT_SCR_CTL);
udelay(10000);
writel(0x301, port_mmio + PORT_SCR_CTL);
udelay(10000);
writel(0x300, port_mmio + PORT_SCR_CTL);
udelay(1000);
/*
* Bring up SATA link.
* SATA link bringup time is usually less than 1 ms; only very

29
u-boot/drivers/clk/rockchip/clk_pll.c
View File

@ -155,8 +155,8 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz,
f_frac = (foutvco % MHZ);
fin_64 = fin_hz;
fin_64 = fin_64 / rate_table->refdiv;
frac_64 = f_frac << 24;
fin_64 = fin_64 / (ulong)rate_table->refdiv;
frac_64 = (ulong)f_frac << 24;
frac_64 = frac_64 / fin_64;
rate_table->frac = frac_64;
if (rate_table->frac > 0)
@ -330,10 +330,10 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
RK3036_PLLCON1_REFDIV_MASK),
(rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |
rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));
if (!rate->dsmpd) {
rk_clrsetreg(base + pll->con_offset + 0x4,
rk_clrsetreg(base + pll->con_offset + 0x4,
RK3036_PLLCON1_DSMPD_MASK,
rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);
if (!rate->dsmpd) {
writel((readl(base + pll->con_offset + 0x8) &
(~RK3036_PLLCON2_FRAC_MASK)) |
(rate->frac << RK3036_PLLCON2_FRAC_SHIFT),
@ -372,7 +372,7 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
{
u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
u32 con = 0, shift, mask;
ulong rate;
ulong rate, p_rate = OSC_HZ / KHZ;
int mode;
con = readl(base + pll->mode_offset);
@ -404,14 +404,14 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
con = readl(base + pll->con_offset + 0x8);
frac = (con & RK3036_PLLCON2_FRAC_MASK) >>
RK3036_PLLCON2_FRAC_SHIFT;
rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
rate = (p_rate * fbdiv / (refdiv * postdiv1 * postdiv2)) * KHZ;
if (dsmpd == 0) {
u64 frac_rate = OSC_HZ * (u64)frac;
u64 frac_rate = p_rate * (u64)frac * KHZ;
do_div(frac_rate, refdiv);
do_div(frac_rate, (u64)refdiv);
frac_rate >>= 24;
do_div(frac_rate, postdiv1);
do_div(frac_rate, postdiv1);
do_div(frac_rate, (u64)postdiv1);
do_div(frac_rate, (u64)postdiv2);
rate += frac_rate;
}
return rate;
@ -491,11 +491,10 @@ static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll,
RK3588_PLLCON1_S_MASK),
(rate->p << RK3588_PLLCON1_P_SHIFT |
rate->s << RK3588_PLLCON1_S_SHIFT));
if (rate->k) {
rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
RK3588_PLLCON2_K_MASK,
rate->k << RK3588_PLLCON2_K_SHIFT);
}
rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
RK3588_PLLCON2_K_MASK,
rate->k << RK3588_PLLCON2_K_SHIFT);
/* Power up */
rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1),
RK3588_PLLCON1_PWRDOWN);

41
u-boot/drivers/clk/rockchip/clk_rk3036.c
View File

@ -255,8 +255,16 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
break;
case HCLK_SDIO:
case SCLK_SDIO:
con = readl(&cru->cru_clksel_con[12]);
mux = (con & SDIO_PLL_MASK) >> SDIO_PLL_SHIFT;
con = readl(&cru->cru_clksel_con[11]);
div = (con & SDIO_DIV_MASK) >> SDIO_DIV_SHIFT;
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->cru_clksel_con[12]);
mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
con = readl(&cru->cru_clksel_con[11]);
div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
break;
default:
@ -296,10 +304,27 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
break;
case HCLK_SDIO:
case SCLK_SDIO:
rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO_PLL_MASK,
SDIO_SEL_24M << SDIO_PLL_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_PLL_MASK | MMC0_DIV_MASK,
mux << MMC0_PLL_SHIFT |
SDIO_DIV_MASK,
(src_clk_div - 1) << SDIO_DIV_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO_PLL_MASK,
mux << SDIO_PLL_SHIFT);
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
MMC0_PLL_MASK,
MMC0_SEL_24M << MMC0_PLL_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_DIV_MASK,
(src_clk_div - 1) << MMC0_DIV_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[12],
MMC0_PLL_MASK,
mux << MMC0_PLL_SHIFT);
break;
default:
return -EINVAL;
@ -464,6 +489,14 @@ static ulong rk3036_clk_get_rate(struct clk *clk)
switch (clk->id) {
case 0 ... 63:
return rkclk_pll_get_rate(priv->cru, clk->id);
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO:
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
return rockchip_mmc_get_clk(priv->cru, gclk_rate,
clk->id);
case SCLK_LCDC:
return rockchip_dclk_lcdc_get_clk(priv->cru, gclk_rate);
case ACLK_LCDC:
@ -487,7 +520,11 @@ static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
case 0 ... 63:
return 0;
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO:
new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
clk->id, rate);
break;

8
u-boot/drivers/clk/rockchip/clk_rk3308.c
View File

@ -974,7 +974,9 @@ static ulong rk3308_clk_get_rate(struct clk *clk)
case SCLK_SPI1:
rate = rk3308_spi_get_clk(clk);
break;
case SCLK_PWM:
case SCLK_PWM0:
case SCLK_PWM1:
case SCLK_PWM2:
rate = rk3308_pwm_get_clk(clk);
break;
case DCLK_VOP:
@ -1059,7 +1061,9 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SPI1:
ret = rk3308_spi_set_clk(clk, rate);
break;
case SCLK_PWM:
case SCLK_PWM0:
case SCLK_PWM1:
case SCLK_PWM2:
ret = rk3308_pwm_set_clk(clk, rate);
break;
case DCLK_VOP:

58
u-boot/drivers/clk/rockchip/clk_rk3528.c
View File

@ -1832,6 +1832,52 @@ U_BOOT_DRIVER(rockchip_rk3528_grf_cru) = {
.probe = rk3528_grfclk_probe,
};
#ifdef CONFIG_SPL_BUILD
#define COREGRF_BASE 0xff300000
#define PVTPLL_CON0_L 0x0
#define PVTPLL_CON0_H 0x4
static int rk3528_cpu_pvtpll_set_rate(struct rk3528_clk_priv *priv, ulong rate)
{
struct rk3528_cru *cru = priv->cru;
u32 length;
if (rate >= 1200000000)
length = 8;
else if (rate >= 1008000000)
length = 11;
else
length = 17;
/* set pclk dbg div to 9 */
rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
9 << RK3528_DIV_PCLK_DBG_SHIFT);
/* set aclk_m_core div to 1 */
rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
1 << RK3528_DIV_ACLK_M_CORE_SHIFT);
/* set ring sel = 1 */
writel(0x07000000 | (1 << 8), COREGRF_BASE + PVTPLL_CON0_L);
/* set length */
writel(0x007f0000 | length, COREGRF_BASE + PVTPLL_CON0_H);
/* enable pvtpll */
writel(0x00020002, COREGRF_BASE + PVTPLL_CON0_L);
/* start monitor */
writel(0x00010001, COREGRF_BASE + PVTPLL_CON0_L);
/* set core mux pvtpll */
writel(0x00010001, &cru->clksel_con[40]);
writel(0x00100010, &cru->clksel_con[39]);
/* set pclk dbg div to 8 */
rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
8 << RK3528_DIV_PCLK_DBG_SHIFT);
return 0;
}
#endif
static int rk3528_clk_init(struct rk3528_clk_priv *priv)
{
int ret;
@ -1866,7 +1912,13 @@ static int rk3528_clk_init(struct rk3528_clk_priv *priv)
if (!ret)
priv->armclk_init_hz = APLL_HZ;
}
#else
if (!rk3528_cpu_pvtpll_set_rate(priv, CPU_PVTPLL_HZ)) {
printf("cpu pvtpll %d KHz\n", CPU_PVTPLL_HZ / 1000);
priv->armclk_init_hz = CPU_PVTPLL_HZ;
}
#elif CONFIG_IS_ENABLED(CLK_SCMI)
if (!priv->armclk_enter_hz) {
struct clk clk;
@ -1882,9 +1934,7 @@ static int rk3528_clk_init(struct rk3528_clk_priv *priv)
printf("Failed to set scmi cpu %dhz\n", CPU_PVTPLL_HZ);
return ret;
} else {
priv->armclk_enter_hz =
rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
priv->cru, APLL);
priv->armclk_enter_hz = CPU_PVTPLL_HZ;
priv->armclk_init_hz = CPU_PVTPLL_HZ;
}
}

8
u-boot/drivers/clk/rockchip/clk_rk3562.c
View File

@ -31,6 +31,8 @@ static struct rockchip_pll_rate_table rk3562_pll_rates[] = {
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(705600000, 2, 235, 4, 1, 0, 3355443),
RK3036_PLL_RATE(611520000, 4, 611, 6, 1, 0, 8724152),
RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
@ -1166,7 +1168,7 @@ static ulong rk3562_vop_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
return DIV_TO_RATE(prate, div);
}
#define RK3562_VOP_PLL_LIMIT_FREQ 600000000
#define RK3562_VOP_PLL_LIMIT_FREQ 594000000
static ulong rk3562_vop_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
ulong rate)
@ -1198,6 +1200,8 @@ static ulong rk3562_vop_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
return rk3562_vop_get_rate(priv, clk_id);
case DCLK_VOP:
div = DIV_ROUND_UP(RK3562_VOP_PLL_LIMIT_FREQ, rate);
if (div % 2)
div = div + 1;
rk_clrsetreg(&cru->clksel_con[30],
DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK,
DCLK_VOP_SEL_VPLL << DCLK_VOP_SEL_SHIFT |
@ -1792,7 +1796,7 @@ static void rk3562_clk_init(struct rk3562_clk_priv *priv)
priv->cru, APLL);
if (!priv->armclk_init_hz) {
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
ret = rk3562_armclk_set_rate(priv, APLL_HZ);
if (!ret)
priv->armclk_init_hz = APLL_HZ;

7
u-boot/drivers/clk/rockchip/clk_rk3568.c
View File

@ -1815,7 +1815,7 @@ static ulong rk3568_dclk_vop_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
return DIV_TO_RATE(parent, div);
}
#define RK3568_VOP_PLL_LIMIT_FREQ 600000000
#define RK3568_VOP_PLL_LIMIT_FREQ 594000000
static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv,
ulong clk_id, ulong rate)
@ -1850,6 +1850,8 @@ static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv,
rk3568_pmu_pll_set_rate(priv, HPLL, div * rate);
} else if (sel == DCLK_VOP_SEL_VPLL) {
div = DIV_ROUND_UP(RK3568_VOP_PLL_LIMIT_FREQ, rate);
if (div % 2)
div = div + 1;
rk_clrsetreg(&cru->clksel_con[conid],
DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK,
(DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT) |
@ -1865,6 +1867,9 @@ static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv,
case DCLK_VOP_SEL_CPLL:
pll_rate = priv->cpll_hz;
break;
case DCLK_VOP_SEL_HPLL:
case DCLK_VOP_SEL_VPLL:
continue;
default:
printf("do not support this vop pll sel\n");
return -EINVAL;

9
u-boot/drivers/clk/rockchip/clk_rk3588.c
View File

@ -1103,7 +1103,7 @@ static ulong rk3588_dclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
return DIV_TO_RATE(parent, div);
}
#define RK3588_VOP_PLL_LIMIT_FREQ 600000000
#define RK3588_VOP_PLL_LIMIT_FREQ 594000000
static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv,
ulong clk_id, ulong rate)
@ -1164,6 +1164,8 @@ static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv,
((div - 1) << div_shift));
} else {
div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
if (div % 2)
div = div + 1;
rk_clrsetreg(&cru->clksel_con[conid],
mask,
DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
@ -2061,7 +2063,10 @@ static int rk3588_clk_probe(struct udevice *dev)
{
struct rk3588_clk_priv *priv = dev_get_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(CLK_SCMI)
struct clk clk;
#endif
priv->sync_kernel = false;
@ -2080,6 +2085,7 @@ static int rk3588_clk_probe(struct udevice *dev)
}
#endif
#if CONFIG_IS_ENABLED(CLK_SCMI)
ret = rockchip_get_scmi_clk(&clk.dev);
if (ret) {
printf("Failed to get scmi clk dev\n");
@ -2110,6 +2116,7 @@ static int rk3588_clk_probe(struct udevice *dev)
ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
if (ret < 0)
printf("Failed to set cpub23\n");
#endif
#endif
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);

3
u-boot/drivers/clk/rockchip/clk_rv1106.c
View File

@ -1131,6 +1131,9 @@ static ulong rv1106_clk_get_rate(struct clk *clk)
rate = rv1106_decom_get_clk(priv);
break;
#endif
case TCLK_WDT_NS:
rate = OSC_HZ;
break;
default:
return -ENOENT;
}

4
u-boot/drivers/core/device.c
View File

@ -510,8 +510,10 @@ int device_probe(struct udevice *dev)
if (ret)
goto fail_uclass;
if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL)
if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL) {
pinctrl_select_state(dev, "init");
pinctrl_select_state(dev, "default");
}
return 0;
fail_uclass:

65
u-boot/drivers/core/uclass.c
View File

@ -503,23 +503,40 @@ int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent,
}
#endif
int uclass_first_device(enum uclass_id id, struct udevice **devp)
/*
* Starting from the given device @dev, return pointer to the first device in
* the uclass that probes successfully in @devp.
*/
static void _uclass_next_device(struct udevice *dev, struct udevice **devp)
{
for (; dev; uclass_find_next_device(&dev)) {
if (!device_probe(dev))
break;
}
*devp = dev;
}
void uclass_first_device(enum uclass_id id, struct udevice **devp)
{
struct udevice *dev;
int ret;
*devp = NULL;
ret = uclass_find_first_device(id, &dev);
if (!dev)
return 0;
return uclass_get_device_tail(dev, ret, devp);
uclass_find_first_device(id, &dev);
_uclass_next_device(dev, devp);
}
void uclass_next_device(struct udevice **devp)
{
struct udevice *dev = *devp;
uclass_find_next_device(&dev);
_uclass_next_device(dev, devp);
}
int uclass_first_device_err(enum uclass_id id, struct udevice **devp)
{
int ret;
ret = uclass_first_device(id, devp);
ret = uclass_first_device_check(id, devp);
if (ret)
return ret;
else if (!*devp)
@ -528,16 +545,17 @@ int uclass_first_device_err(enum uclass_id id, struct udevice **devp)
return 0;
}
int uclass_next_device(struct udevice **devp)
int uclass_next_device_err(struct udevice **devp)
{
struct udevice *dev = *devp;
int ret;
*devp = NULL;
ret = uclass_find_next_device(&dev);
if (!dev)
return 0;
return uclass_get_device_tail(dev, ret, devp);
ret = uclass_next_device_check(devp);
if (ret)
return ret;
else if (!*devp)
return -ENODEV;
return 0;
}
int uclass_first_device_check(enum uclass_id id, struct udevice **devp)
@ -567,6 +585,23 @@ int uclass_next_device_check(struct udevice **devp)
return device_probe(*devp);
}
int uclass_first_device_drvdata(enum uclass_id id, ulong driver_data,
struct udevice **devp)
{
struct udevice *dev;
struct uclass *uc;
uclass_id_foreach_dev(id, dev, uc) {
if (dev_get_driver_data(dev) == driver_data) {
*devp = dev;
return device_probe(dev);
}
}
return -ENODEV;
}
int uclass_bind_device(struct udevice *dev, bool after_u_boot_dev)
{
struct uclass *uc;

2
u-boot/drivers/cpu/amp.its
View File

@ -99,6 +99,8 @@
thumb = <0>;
hyp = <0>;
udelay = <1000000>;
load = <0x2000000>; // optional
load_c = <0x4000000>; // optional
};
};
};

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