/* * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "rk312x.dtsi" / { compatible = "rockchip,rk3128"; rng: rng@100fc000 { compatible = "rockchip,cryptov1-rng"; reg = <0x100fc000 0x4000>; clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; clock-names = "clk_crypto", "hclk_crypto"; assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; assigned-clock-rates = <150000000>, <100000000>; resets = <&cru SRST_CRYPTO>; reset-names = "reset"; status = "disabled"; }; qos_ebc: qos@1012f080 { compatible = "syscon"; reg = <0x1012f080 0x20>; }; hdmi: hdmi@20034000 { compatible = "rockchip,rk3128-inno-hdmi"; reg = <0x20034000 0x4000>; interrupts = ; clocks = <&cru ACLK_VIO0>, <&cru PCLK_HDMI>; clock-names = "aclk", "pclk"; rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; #address-cells = <1>; #size-cells = <0>; #sound-dai-cells = <0>; status = "disabled"; hdmi_in: port { #address-cells = <1>; #size-cells = <0>; hdmi_in_vop: endpoint@0 { reg = <0>; remote-endpoint = <&vop_out_hdmi>; }; }; }; }; &codec { /* * Override the i2s_clk since codec connects to i2s_8ch in rk3128, * which is different from rk3126. */ clock-names = "g_pclk_acodec", "i2s_clk"; clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S0>; }; &cpu0_opp_table { rockchip,leakage-scaling-sel = < 1 254 0 >; rockchip,leakage-voltage-sel = < 1 14 0 15 35 1 36 254 2 >; opp-216000000 { opp-hz = /bits/ 64 <216000000>; opp-microvolt = <950000 950000 1425000>; opp-microvolt-L0 = <950000 950000 1425000>; opp-microvolt-L1 = <950000 950000 1425000>; opp-microvolt-L2 = <950000 950000 1425000>; clock-latency-ns = <40000>; }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000 950000 1425000>; opp-microvolt-L0 = <950000 950000 1425000>; opp-microvolt-L1 = <950000 950000 1425000>; opp-microvolt-L2 = <950000 950000 1425000>; clock-latency-ns = <40000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt-L0 = <950000 950000 1425000>; opp-microvolt-L1 = <950000 950000 1425000>; opp-microvolt-L2 = <950000 950000 1425000>; clock-latency-ns = <40000>; }; opp-696000000 { opp-hz = /bits/ 64 <696000000>; opp-microvolt = <1150000 1150000 1425000>; opp-microvolt-L0 = <975000 975000 1425000>; opp-microvolt-L1 = <975000 975000 1425000>; opp-microvolt-L2 = <975000 975000 1425000>; clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1075000 1075000 1425000>; opp-microvolt-L0 = <1075000 1075000 1425000>; opp-microvolt-L1 = <1050000 1050000 1425000>; opp-microvolt-L2 = <1000000 1000000 1425000>; clock-latency-ns = <40000>; opp-suspend; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1425000>; opp-microvolt-L0 = <1200000 1200000 1425000>; opp-microvolt-L1 = <1175000 1175000 1425000>; opp-microvolt-L2 = <1125000 1125000 1425000>; clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1325000 1325000 1425000>; opp-microvolt-L0 = <1325000 1325000 1425000>; opp-microvolt-L1 = <1300000 1300000 1425000>; opp-microvolt-L2 = <1250000 1250000 1425000>; clock-latency-ns = <40000>; }; }; &pd_vio { pm_qos = <&qos_rga>, <&qos_ebc>, <&qos_iep>, <&qos_lcdc0>, <&qos_vip0>; }; &sdmmc_pwren { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; }; &video_phy { status = "okay"; }; &vop_mmu { rockchip,skip-mmu-read; }; &vop_out { #address-cells = <1>; #size-cells = <0>; vop_out_dsi: endpoint@0 { reg = <0>; remote-endpoint = <&dsi_in_vop>; }; vop_out_lvds: endpoint@1 { reg = <1>; remote-endpoint = <&lvds_in_vop>; }; vop_out_hdmi: endpoint@2 { reg = <2>; remote-endpoint = <&hdmi_in_vop>; }; };