/* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include "rk3288-dram-default-timing.dtsi" #include / { chosen: chosen { bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M"; }; cpuinfo { compatible = "rockchip,cpuinfo"; nvmem-cells = <&efuse_id>; nvmem-cell-names = "id"; }; /delete-node/ dmc@ff610000; dfi: dfi { compatible = "rockchip,rk3288-dfi"; rockchip,pmu = <&pmu>; rockchip,grf = <&grf>; status = "disabled"; }; dmc: dmc { compatible = "rockchip,rk3288-dmc"; devfreq-events = <&dfi>; clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>, <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>, <&cru PCLK_DDRUPCTL1>; clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0", "pclk_phy1", "pclk_upctl1"; upthreshold = <55>; downdifferential = <10>; operating-points-v2 = <&dmc_opp_table>; vop-dclk-mode = <0>; min-cpu-freq = <600000>; rockchip,ddr_timing = <&ddr_timing>; system-status-freq = < /*system status freq(KHz)*/ SYS_STATUS_NORMAL 396000 SYS_STATUS_REBOOT 396000 SYS_STATUS_SUSPEND 192000 SYS_STATUS_VIDEO_1080P 300000 SYS_STATUS_VIDEO_4K 528000 SYS_STATUS_VIDEO_4K_10B 528000 SYS_STATUS_PERFORMANCE 528000 SYS_STATUS_BOOST 396000 SYS_STATUS_DUALVIEW 528000 SYS_STATUS_ISP 528000 >; auto-min-freq = <396000>; auto-freq-en = <0>; status = "diasbled"; }; dmc_opp_table: opp_table2 { compatible = "operating-points-v2"; opp-192000000 { opp-hz = /bits/ 64 <192000000>; opp-microvolt = <1100000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1100000>; }; opp-396000000 { opp-hz = /bits/ 64 <396000000>; opp-microvolt = <1100000>; }; opp-528000000 { opp-hz = /bits/ 64 <528000000>; opp-microvolt = <1150000>; }; }; reserved-memory { ramoops: ramoops@8000000 { compatible = "ramoops"; reg = <0x0 0x8000000 0x0 0xF0000>; record-size = <0x20000>; console-size = <0x80000>; ftrace-size = <0x00000>; pmsg-size = <0x50000>; }; drm_logo: drm-logo@00000000 { compatible = "rockchip,drm-logo"; reg = <0x0 0x0 0x0 0x0>; }; }; fiq-debugger { compatible = "rockchip,fiq-debugger"; interrupts = ; rockchip,serial-id = <2>; rockchip,wake-irq = <0>; rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ pinctrl-names = "default"; pinctrl-0 = <&uart2_xfer>; }; firmware { optee: optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; /delete-node/ timer@ff810000; display-subsystem { status = "okay"; ports = <&vopb_out>, <&vopl_out>; logo-memory-region = <&drm_logo>; route { route_edp: route-edp { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_edp>; }; route_dsi0: route-dsi0 { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_dsi0>; }; route_lvds: route-lvds { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_lvds>; }; route_hdmi: route-hdmi { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopb_out_hdmi>; }; route_rgb: route-rgb { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_rgb>; }; }; }; nandc0: nandc@ff400000 { compatible = "rockchip,rk-nandc"; reg = <0x0 0xff400000 0x0 0x4000>; interrupts = ; nandc_id = <0>; clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>; clock-names = "clk_nandc", "hclk_nandc"; status = "okay"; }; hdmi_analog_sound: hdmi-analog-sound { status = "disabled"; compatible = "rockchip,rk3288-hdmi-analog", "rockchip,rk3368-hdmi-analog"; rockchip,model = "rockchip,rt5640-codec"; rockchip,cpu = <&i2s>; //rockchip,codec = <&rt5640>, <&hdmi>; rockchip,codec = <&hdmi>; rockchip,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; rockchip,routing = "MIC1", "Microphone Jack", "MIC2", "Microphone Jack", "Microphone Jack", "micbias1", "Headphone Jack", "HPOL", "Headphone Jack", "HPOR"; }; }; &dmac_bus_s { /* change to non-secure dmac */ reg = <0x0 0xff600000 0x0 0x4000>; }; &dsi0 { panel@0 { reg = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; panel_in_dsi: endpoint { remote-endpoint = <&dsi_out_panel>; }; }; }; }; ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; dsi_out_panel: endpoint { remote-endpoint = <&panel_in_dsi>; }; }; }; }; &efuse { compatible = "rockchip,rk3288-secure-efuse"; }; &iep { status = "okay"; }; &iep_mmu { status = "okay"; }; &dsi0_in_vopb { status = "disabled"; }; &edp_in_vopb { status = "disabled"; }; &hdmi_in_vopl { status = "disabled"; }; &mpp_srv { status = "okay"; }; &hevc { status = "okay"; }; &hevc_mmu { status = "okay"; }; &rga { compatible = "rockchip,rga2"; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; clock-names = "aclk_rga", "hclk_rga", "clk_rga"; assigned-clocks = <&cru ACLK_RGA>, <&cru SCLK_RGA>; assigned-clock-rates = <300000000>, <300000000>; status = "okay"; }; &rng { status = "okay"; }; &uart2 { status = "disabled"; }; &pinctrl { buttons { pwrbtn: pwrbtn { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; &vdpu { status = "okay"; }; &vepu { status = "okay"; }; &vopb { support-multi-area; }; &vopl { support-multi-area; }; &video_phy { status = "okay"; }; &vpu_mmu { status = "okay"; };