/* * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: (GPL-2.0+ OR MIT). */ #include #include "rk3288-dram-default-timing.dtsi" / { aliases { mshc0 = &emmc; mshc1 = &sdmmc; mshc2 = &sdio0; mshc3 = &sdio1; }; chosen { bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait"; }; /delete-node/ dmc@ff610000; dfi: dfi { compatible = "rockchip,rk3288-dfi"; rockchip,pmu = <&pmu>; rockchip,grf = <&grf>; status = "disabled"; }; dmc: dmc { compatible = "rockchip,rk3288-dmc"; devfreq-events = <&dfi>; clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>, <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>, <&cru PCLK_DDRUPCTL1>; clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0", "pclk_phy1", "pclk_upctl1"; upthreshold = <55>; downdifferential = <10>; operating-points-v2 = <&dmc_opp_table>; vop-dclk-mode = <0>; min-cpu-freq = <600000>; rockchip,ddr_timing = <&ddr_timing>; system-status-freq = < /*system status freq(KHz)*/ SYS_STATUS_NORMAL 396000 SYS_STATUS_REBOOT 396000 SYS_STATUS_SUSPEND 192000 SYS_STATUS_VIDEO_1080P 300000 SYS_STATUS_VIDEO_4K 396000 SYS_STATUS_VIDEO_4K_10B 528000 SYS_STATUS_PERFORMANCE 528000 SYS_STATUS_BOOST 396000 SYS_STATUS_DUALVIEW 396000 SYS_STATUS_ISP 396000 >; auto-min-freq = <396000>; auto-freq-en = <0>; status = "diasbled"; }; dmc_opp_table: opp_table2 { compatible = "operating-points-v2"; opp-192000000 { opp-hz = /bits/ 64 <192000000>; opp-microvolt = <1100000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1100000>; }; opp-396000000 { opp-hz = /bits/ 64 <396000000>; opp-microvolt = <1100000>; }; opp-528000000 { opp-hz = /bits/ 64 <528000000>; opp-microvolt = <1150000>; }; }; reserved-memory { ramoops_mem: ramoops@8000000 { reg = <0x0 0x8000000 0x0 0xF0000>; }; drm_logo: drm-logo@00000000 { compatible = "rockchip,drm-logo"; reg = <0x0 0x0 0x0 0x0>; }; }; fiq-debugger { compatible = "rockchip,fiq-debugger"; interrupts = ; rockchip,serial-id = <2>; rockchip,wake-irq = <0>; rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ pinctrl-names = "default"; pinctrl-0 = <&uart2_xfer>; }; /delete-node/ timer@ff810000; display-subsystem { status = "okay"; ports = <&vopb_out>, <&vopl_out>; logo-memory-region = <&drm_logo>; route { route_hdmi: route-hdmi { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopb_out_hdmi>; }; route_edp: route-edp { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_edp>; }; route_dsi0: route-dsi0 { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_dsi0>; }; route_lvds: route-lvds { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_lvds>; }; route_rgb: route-rgb { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <&vopl_out_rgb>; }; }; }; }; &dmac_bus_s { /* change to non-secure dmac */ reg = <0x0 0xff600000 0x0 0x4000>; }; &efuse { compatible = "rockchip,rk3288-secure-efuse"; }; &mpp_srv { status = "okay"; }; &hevc { status = "okay"; }; &hevc_mmu { status = "okay"; }; &iep { status = "okay"; }; &iep_mmu { status = "okay"; }; &rga { compatible = "rockchip,rga2"; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; clock-names = "aclk_rga", "hclk_rga", "clk_rga"; status = "okay"; }; &rng { status = "okay"; }; &uart2 { status = "disabled"; }; &vdpu { status = "okay"; }; &vepu { status = "okay"; }; &vpu_mmu { status = "okay"; }; &video_phy { status = "okay"; };