/* * SPDX-License-Identifier: GPL-2.0+ * * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ /dts-v1/; #include "rk3568.dtsi" #include "rk3568-u-boot.dtsi" #include / { model = "Rockchip RK3568 Evaluation Board"; compatible = "rockchip,rk3568-evb", "rockchip,rk3568"; adc-keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; keyup-threshold-microvolt = <1800000>; u-boot,dm-spl; status = "okay"; volumeup-key { u-boot,dm-spl; linux,code = ; label = "volume up"; press-threshold-microvolt = <9>; }; }; }; &gmac0 { phy-mode = "rgmii"; clock_in_out = "output"; snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; snps,reset-active-low; /* Reset time is 20ms, 100ms for rtl8211f */ snps,reset-delays-us = <0 20000 100000>; assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; assigned-clock-rates = <0>, <125000000>; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus>; tx_delay = <0x3c>; rx_delay = <0x2f>; phy-handle = <&rgmii_phy0>; status = "disabled"; }; &gmac1 { phy-mode = "rgmii"; clock_in_out = "output"; snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; snps,reset-active-low; /* Reset time is 20ms, 100ms for rtl8211f */ snps,reset-delays-us = <0 20000 100000>; assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; assigned-clock-rates = <0>, <125000000>; pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_rgmii_bus>; tx_delay = <0x4f>; rx_delay = <0x26>; phy-handle = <&rgmii_phy1>; status = "disabled"; }; &mdio0 { rgmii_phy0: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; }; }; &mdio1 { rgmii_phy1: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; }; }; &crypto { status = "okay"; }; &uart2 { status = "okay"; };