// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 *
 */

#include <dt-bindings/display/drm_mipi_dsi.h>
#include "rk3399-vop-clk-set.dtsi"

/ {
	compatible = "rockchip,linux", "rockchip,rk3399";

	aliases {
		mmc0 = &sdhci;
		mmc1 = &sdmmc;
		mmc2 = &sdio0;
	};

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		drm_logo: drm-logo@00000000 {
			compatible = "rockchip,drm-logo";
			reg = <0x0 0x0 0x0 0x0>;
		};

		ramoops_mem: region@110000 {
			reg = <0x0 0x110000 0x0 0xf0000>;
			reg-names = "ramoops_mem";
		};
	};

	ramoops: ramoops {
		compatible = "ramoops";
		record-size = <0x0 0x40000>;
		console-size = <0x0 0x80000>;
		ftrace-size = <0x0 0x00000>;
		pmsg-size = <0x0 0x00000>;
		memory-region = <&ramoops_mem>;
	};

	fiq_debugger: fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,wake-irq = <0>;
		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2c_xfer>;
	};

	cif_isp0: cif_isp@ff910000 {
		compatible = "rockchip,rk3399-cif-isp";
		rockchip,grf = <&grf>;
		reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
		reg-names = "register", "dsihost-register";
		clocks =
			<&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
			<&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
			<&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>,
			<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
			<&cru SCLK_MIPIDPHY_REF>;
		clock-names =
			"aclk_isp0_noc", "aclk_isp0_wrapper",
			"hclk_isp0_noc", "hclk_isp0_wrapper",
			"clk_isp0", "pclk_dphyrx",
			"clk_cif_out", "clk_cif_pll",
			"pclk_dphy_ref";
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "cif_isp10_irq";
		power-domains = <&power RK3399_PD_ISP0>;
		rockchip,isp,iommu-enable = <1>;
		iommus = <&isp0_mmu>;
		status = "disabled";
	};

	cif_isp1: cif_isp@ff920000 {
		compatible = "rockchip,rk3399-cif-isp";
		rockchip,grf = <&grf>;
		reg = <0x0 0xff920000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
		reg-names = "register", "dsihost-register";
		clocks =
			<&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
			<&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
			<&cru SCLK_ISP1>, <&cru PCLK_ISP1_WRAPPER>,
			<&cru SCLK_DPHY_TX1RX1_CFG>,
			<&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>,
			<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
			<&cru SCLK_MIPIDPHY_REF>;
		clock-names =
			"aclk_isp1_noc", "aclk_isp1_wrapper",
			"hclk_isp1_noc", "hclk_isp1_wrapper",
			"clk_isp1", "pclkin_isp1",
			"pclk_dphytxrx",
			"pclk_mipi_dsi","mipi_dphy_cfg",
			"clk_cif_out", "clk_cif_pll",
			"pclk_dphy_ref";
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "cif_isp10_irq";
		power-domains = <&power RK3399_PD_ISP1>;
		rockchip,isp,iommu-enable = <1>;
		iommus = <&isp1_mmu>;
		status = "disabled";
	};

	rga: rga@ff680000 {
		compatible = "rockchip,rga2";
		dev_mode = <1>;
		reg = <0x0 0xff680000 0x0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		power-domains = <&power RK3399_PD_RGA>;
		status = "okay";
	};
};

&display_subsystem {
	status = "disabled";

	ports = <&vopb_out>, <&vopl_out>;
	logo-memory-region = <&drm_logo>;

	route {
		route_hdmi: route-hdmi {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vopb_out_hdmi>;
		};

		route_dsi: route-dsi {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vopl_out_dsi>;
		};

		route_edp: route-edp {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vopl_out_edp>;
		};
	};
};

&edp {
	/delete-property/pinctrl-names;
	/delete-property/pinctrl-0;
};

&iep {
	status = "okay";
};

&iep_mmu {
	status = "okay";
};

&mpp_srv {
	status = "okay";
};

&pvtm {
	status = "okay";
};

&rkvdec {
	status = "okay";
	/* 0 means ion, 1 means drm */
	//allocator = <0>;
};

&vdec_mmu {
	status = "okay";
};

&vdpu {
	status = "okay";
};

&vepu {
	status = "okay";
};

&vpu_mmu {
	status = "okay";
};

&uart2 {
	status = "disabled";
};

&pinctrl {
	isp {
		cif_clkout: cif-clkout {
			rockchip,pins =
				/* cif_clkout */
				<2 RK_PB3 3 &pcfg_pull_none>;
		};

		isp_dvp_d0d7: isp-dvp-d0d7 {
			rockchip,pins =
				<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
				/* cif_clkout */
				<2 RK_PB3 3 &pcfg_pull_none>,
				/* cif_data0 */
				<2 RK_PA0 3 &pcfg_pull_none>,
				/* cif_data1 */
				<2 RK_PA1 3 &pcfg_pull_none>,
				/* cif_data2 */
				<2 RK_PA2 3 &pcfg_pull_none>,
				/* cif_data3 */
				<2 RK_PA3 3 &pcfg_pull_none>,
				/* cif_data4 */
				<2 RK_PA4 3 &pcfg_pull_none>,
				/* cif_data5 */
				<2 RK_PA5 3 &pcfg_pull_none>,
				/* cif_data6 */
				<2 RK_PA6 3 &pcfg_pull_none>,
				/* cif_data7 */
				<2 RK_PA7 3 &pcfg_pull_none>,
				/* cif_sync */
				<2 RK_PB0 3 &pcfg_pull_none>,
				/* cif_href */
				<2 RK_PB1 3 &pcfg_pull_none>,
				/* cif_clkin */
				<2 RK_PB2 3 &pcfg_pull_none>;
		};

		isp_shutter: isp-shutter {
			rockchip,pins =
				/* SHUTTEREN */
				<1 RK_PA1 1 &pcfg_pull_none>,
				/* SHUTTERTRIG */
				<1 RK_PA0 1 &pcfg_pull_none>;
		};

		isp_flash_trigger: isp-flash-trigger {
			/* ISP_FLASHTRIGOU */
			rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
		};

		isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
			/* ISP_FLASHTRIGOU */
			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	cam_pins {
		cam0_default_pins: cam0-default-pins {
			rockchip,pins =
				<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
				<2 RK_PB3 3 &pcfg_pull_none>;
		};
		cam0_sleep_pins: cam0-sleep-pins {
			rockchip,pins =
				<4 RK_PD3 3 &pcfg_pull_none>,
				<2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};