// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2020 Rockchip Electronics Co., Ltd. */ /dts-v1/; #include #include #include "rk3566.dtsi" #include "rk3566-evb.dtsi" / { model = "Rockchip RK3566 EVB MIPITEST V10 Board"; compatible = "rockchip,rk3566-evb-mipitest-v10", "rockchip,rk3566"; vcc3v3_pcie: gpio-regulator { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; startup-delay-us = <5000>; vin-supply = <&dc_12v>; }; rk_headset: rk-headset { compatible = "rockchip_headset"; headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&hp_det>; }; vcc3v3_vga: vcc3v3-vga { compatible = "regulator-fixed"; regulator-name = "vcc3v3_vga"; regulator-always-on; regulator-boot-on; gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vcc3v3_sys>; }; vcc_camera: vcc-camera-regulator { compatible = "regulator-fixed"; gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&camera_pwr>; regulator-name = "vcc_camera"; enable-active-high; regulator-always-on; regulator-boot-on; }; }; &audiopwmout_diff { status = "disabled"; }; &combphy1_usq { status = "okay"; }; &combphy2_psq { status = "okay"; }; &csi2_dphy_hw { status = "okay"; }; &csi2_dphy1 { status = "okay"; /* * dphy1 only used for split mode, * can be used concurrently with dphy2 * full mode and split mode are mutually exclusive */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; dphy1_in: endpoint@1 { reg = <1>; remote-endpoint = <&ov5695_out>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; dphy1_out: endpoint@1 { reg = <1>; remote-endpoint = <&isp0_in>; }; }; }; }; &csi2_dphy2 { status = "okay"; /* * dphy2 only used for split mode, * can be used concurrently with dphy1 * full mode and split mode are mutually exclusive */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; dphy2_in: endpoint@1 { reg = <1>; remote-endpoint = <&ov02k10_out>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; dphy2_out: endpoint@1 { reg = <1>; remote-endpoint = <&mipi_csi2_input>; }; }; }; }; &dig_acodec { status = "disabled"; rockchip,pwm-output-mode; pinctrl-names = "default"; pinctrl-0 = <&audiopwm_loutp &audiopwm_loutn &audiopwm_routp &audiopwm_routn >; }; /* * video_phy0 needs to be enabled * when dsi0 is enabled */ &dsi0 { status = "okay"; }; &dsi0_in_vp0 { status = "disabled"; }; &dsi0_in_vp1 { status = "okay"; }; &dsi0_panel { power-supply = <&vcc3v3_lcd0_n>; reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&lcd0_rst_gpio>; }; /* * video_phy1 needs to be enabled * when dsi1 is enabled */ &dsi1 { status = "disabled"; }; &dsi1_in_vp0 { status = "disabled"; }; &dsi1_in_vp1 { status = "disabled"; }; &dsi1_panel { power-supply = <&vcc3v3_lcd1_n>; reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&lcd1_rst_gpio>; }; &edp { hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; status = "okay"; }; &edp_phy { status = "okay"; }; &edp_in_vp0 { status = "okay"; }; &edp_in_vp1 { status = "disabled"; }; /* * power-supply should switche to vcc3v3_lcd1_n * when mipi panel is connected to dsi1. */ >1x { status = "disabled"; power-supply = <&vcc3v3_lcd0_n>; }; &hdmi { status = "disabled"; }; &i2c2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c2m1_xfer>; /* split mode: lane0/1 */ ov5695: ov5695@36 { status = "okay"; compatible = "ovti,ov5695"; reg = <0x36>; clocks = <&cru CLK_CAM0_OUT>; clock-names = "xvclk"; power-domains = <&power RK3568_PD_VI>; pinctrl-names = "default"; pinctrl-0 = <&cam_clkout0>; reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; pwdn-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ rockchip,camera-module-index = <0>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "TongJu"; rockchip,camera-module-lens-name = "CHT842-MD"; port { ov5695_out: endpoint { remote-endpoint = <&dphy1_in>; data-lanes = <1 2>; }; }; }; ov02k10: ov02k10@36 { status = "okay"; compatible = "ovti,ov02k10"; reg = <0x36>; clocks = <&cru CLK_CAM1_OUT>; clock-names = "xvclk"; pinctrl-names = "default"; pinctrl-0 = <&cam_clkout1>; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; rockchip,camera-module-index = <0>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "TongJu"; rockchip,camera-module-lens-name = "CHT842-MD"; port { ov02k10_out: endpoint { remote-endpoint = <&dphy2_in>; data-lanes = <1 2>; }; }; }; }; &i2s3_2ch { status = "disabled"; }; &mipi_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&dphy2_out>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in>; data-lanes = <1 2>; }; }; }; }; &video_phy0 { status = "okay"; }; &video_phy1 { status = "disabled"; }; &pcie2x1 { reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "disabled"; }; &pdm { status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&pdmm1_clk1 &pdmm1_sdi1 &pdmm1_sdi2 &pdmm1_sdi3>; }; &pdmics { status = "disabled"; }; &pdm_mic_array { status = "disabled"; }; &rkcif { status = "okay"; }; &rkcif_mipi_lvds { status = "okay"; port { cif_mipi_in: endpoint { remote-endpoint = <&mipi_csi2_output>; data-lanes = <1 2>; }; }; }; &rkcif_mmu { status = "okay"; }; &rkisp { status = "okay"; }; &rkisp_mmu { status = "okay"; }; &rkisp_vir0 { status = "okay"; port { #address-cells = <1>; #size-cells = <0>; isp0_in: endpoint@0 { reg = <0>; remote-endpoint = <&dphy1_out>; }; }; }; &route_dsi0 { status = "okay"; connect = <&vp1_out_dsi0>; }; &sdmmc2 { max-frequency = <150000000>; no-sd; no-mmc; bus-width = <4>; disable-wp; cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; sd-uhs-sdr104; status = "okay"; }; &uart1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; }; &u2phy1_host { status = "disabled"; }; &u2phy1_otg { status = "disabled"; }; &usb2phy1 { status = "disabled"; }; &usb_host1_ohci { status = "disabled"; }; &vcc3v3_lcd0_n { gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; enable-active-high; }; &vcc3v3_lcd1_n { gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; enable-active-high; }; &wireless_bluetooth { uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "rts_gpio"; pinctrl-0 = <&uart1m1_rtsn>; pinctrl-1 = <&uart1_gpios>; BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; status = "disabled"; }; &wireless_wlan { status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_irq>; WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; }; &pinctrl { cam { camera_pwr: camera-pwr { rockchip,pins = /* camera power en */ <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; headphone { hp_det: hp-det { rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; }; }; lcd0 { lcd0_rst_gpio: lcd0-rst-gpio { rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; lcd1 { lcd1_rst_gpio: lcd1-rst-gpio { rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; wireless-wlan { wifi_host_wake_irq: wifi-host-wake-irq { rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; }; }; wireless-bluetooth { uart1_gpios: uart1-gpios { rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; };