// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
 *
 */

/ {
	chosen: chosen {
		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,wake-irq = <0>;
		/* If enable uart uses irq instead of fiq */
		rockchip,irq-mode-enable = <1>;
		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2m0_xfer>;
		status = "okay";
	};

	debug: debug@fd904000 {
		compatible = "rockchip,debug";
		reg = <0x0 0xfd904000 0x0 0x1000>,
			<0x0 0xfd905000 0x0 0x1000>,
			<0x0 0xfd906000 0x0 0x1000>,
			<0x0 0xfd907000 0x0 0x1000>;
	};

	cspmu: cspmu@fd90c000 {
		compatible = "rockchip,cspmu";
		reg = <0x0 0xfd90c000 0x0 0x1000>,
			<0x0 0xfd90d000 0x0 0x1000>,
			<0x0 0xfd90e000 0x0 0x1000>,
			<0x0 0xfd90f000 0x0 0x1000>;
	};
};

&reserved_memory {
	ramoops: ramoops@110000 {
		compatible = "ramoops";
		reg = <0x0 0x110000 0x0 0xf0000>;
		record-size = <0x20000>;
		console-size = <0x80000>;
		ftrace-size = <0x00000>;
		pmsg-size = <0x50000>;
	};
};

&rng {
	status = "okay";
};