// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2021 Rockchip Electronics Co., Ltd. * */ &csi2_dcphy0 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_in_ucam0: endpoint@1 { reg = <1>; remote-endpoint = <&imx464_out0>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; csidcphy0_out: endpoint@0 { reg = <0>; remote-endpoint = <&mipi0_csi2_input>; }; }; }; }; &csi2_dcphy1 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_in_ucam1: endpoint@1 { reg = <1>; remote-endpoint = <&imx464_out1>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; csidcphy1_out: endpoint@0 { reg = <0>; remote-endpoint = <&mipi1_csi2_input>; }; }; }; }; &csi2_dphy0_hw { status = "okay"; }; &csi2_dphy1_hw { status = "okay"; }; &csi2_dphy1 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_in_ucam2: endpoint@1 { reg = <1>; remote-endpoint = <&imx464_out2>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; csidphy1_out: endpoint@0 { reg = <0>; remote-endpoint = <&mipi2_csi2_input>; }; }; }; }; &csi2_dphy2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_in_ucam3: endpoint@1 { reg = <1>; remote-endpoint = <&imx464_out3>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; csidphy2_out: endpoint@0 { reg = <0>; remote-endpoint = <&mipi3_csi2_input>; }; }; }; }; &csi2_dphy4 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_in_ucam4: endpoint@1 { reg = <1>; remote-endpoint = <&imx464_out4>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; csidphy4_out: endpoint@0 { reg = <0>; remote-endpoint = <&mipi4_csi2_input>; }; }; }; }; &csi2_dphy5 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_in_ucam5: endpoint@1 { reg = <1>; remote-endpoint = <&imx464_out5>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; csidphy5_out: endpoint@0 { reg = <0>; remote-endpoint = <&mipi5_csi2_input>; }; }; }; }; &i2c3 { status = "okay"; /* module 77/79 0x1a 78/80 0x36 */ imx464_2: imx464-2@1a { compatible = "sony,imx464"; status = "okay"; reg = <0x1a>; clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; clock-names = "xvclk"; power-domains = <&power RK3588_PD_VI>; pinctrl-names = "default"; pinctrl-0 = <&mipim0_camera3_clk>; avdd-supply = <&vcc_mipicsi0>; pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; rockchip,camera-module-index = <2>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "CMK-OT1980-PX1"; rockchip,camera-module-lens-name = "SHG102"; port { imx464_out2: endpoint { remote-endpoint = <&mipi_in_ucam2>; data-lanes = <1 2>; }; }; }; imx464_3: imx464-3@36 { compatible = "sony,imx464"; status = "okay"; reg = <0x36>; clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; clock-names = "xvclk"; power-domains = <&power RK3588_PD_VI>; avdd-supply = <&vcc_mipicsi0>; pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; rockchip,camera-module-index = <3>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "CMK-OT1980-PX1"; rockchip,camera-module-lens-name = "SHG102"; port { imx464_out3: endpoint { remote-endpoint = <&mipi_in_ucam3>; data-lanes = <1 2>; }; }; }; }; &i2c4 { status = "okay"; pinctrl-0 = <&i2c4m3_xfer>; /* 77/79 0x1a 78/80 0x36 */ imx464_4: imx464-4@1a { compatible = "sony,imx464"; status = "okay"; reg = <0x1a>; clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; clock-names = "xvclk"; power-domains = <&power RK3588_PD_VI>; pinctrl-names = "default"; pinctrl-0 = <&mipim0_camera4_clk>; avdd-supply = <&vcc_mipicsi1>; pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; rockchip,camera-module-index = <0>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "CMK-OT1980-PX1"; rockchip,camera-module-lens-name = "SHG102"; port { imx464_out4: endpoint { remote-endpoint = <&mipi_in_ucam4>; data-lanes = <1 2>; }; }; }; imx464_5: imx464-5@36 { compatible = "sony,imx464"; status = "okay"; reg = <0x36>; clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; clock-names = "xvclk"; power-domains = <&power RK3588_PD_VI>; avdd-supply = <&vcc_mipicsi1>; pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; rockchip,camera-module-index = <1>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "CMK-OT1980-PX1"; rockchip,camera-module-lens-name = "SHG102"; port { imx464_out5: endpoint { remote-endpoint = <&mipi_in_ucam5>; data-lanes = <1 2>; }; }; }; }; &i2c5 { status = "okay"; /* 77/79 0x1a 78/80 0x36 */ imx464_0: imx464-0@1a { compatible = "sony,imx464"; status = "okay"; reg = <0x1a>; clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; clock-names = "xvclk"; power-domains = <&power RK3588_PD_VI>; pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mipim0_camera1_clk>; avdd-supply = <&vcc_mipidcphy0>; rockchip,camera-module-index = <4>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "CMK-OT1980-PX1"; rockchip,camera-module-lens-name = "SHG102"; port { imx464_out0: endpoint { remote-endpoint = <&mipi_in_ucam0>; data-lanes = <1 2>; }; }; }; imx464_1: imx464-1@36 { compatible = "sony,imx464"; status = "okay"; reg = <0x36>; clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; clock-names = "xvclk"; power-domains = <&power RK3588_PD_VI>; pinctrl-names = "default"; pinctrl-0 = <&mipim0_camera2_clk>; pwdn-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; avdd-supply = <&vcc_mipidcphy0>; rockchip,camera-module-index = <5>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "CMK-OT1980-PX1"; rockchip,camera-module-lens-name = "SHG102"; port { imx464_out1: endpoint { remote-endpoint = <&mipi_in_ucam1>; data-lanes = <1 2>; }; }; }; }; &mipi_dcphy0 { status = "okay"; }; &mipi_dcphy1 { status = "okay"; }; &mipi0_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi0_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&csidcphy0_out>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi0_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in0>; }; }; }; }; &mipi1_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi1_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&csidcphy1_out>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi1_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in1>; }; }; }; }; &mipi2_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi2_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&csidphy1_out>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi2_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in2>; }; }; }; }; &mipi3_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi3_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&csidphy2_out>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi3_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in3>; }; }; }; }; &mipi4_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi4_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&csidphy4_out>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi4_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in4>; }; }; }; }; &mipi5_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi5_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&csidphy5_out>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi5_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in5>; }; }; }; }; &rkcif { status = "okay"; }; &rkcif_mipi_lvds { status = "okay"; port { cif_mipi_in0: endpoint { remote-endpoint = <&mipi0_csi2_output>; }; }; }; &rkcif_mipi_lvds_sditf { status = "okay"; port { mipi_lvds_sditf: endpoint { remote-endpoint = <&isp0_vir0>; }; }; }; &rkcif_mipi_lvds1 { status = "okay"; port { cif_mipi_in1: endpoint { remote-endpoint = <&mipi1_csi2_output>; }; }; }; &rkcif_mipi_lvds1_sditf { status = "okay"; port { mipi1_lvds_sditf: endpoint { remote-endpoint = <&isp1_vir0>; }; }; }; &rkcif_mipi_lvds2 { status = "okay"; port { cif_mipi_in2: endpoint { remote-endpoint = <&mipi2_csi2_output>; }; }; }; &rkcif_mipi_lvds2_sditf { status = "okay"; port { mipi2_lvds_sditf: endpoint { remote-endpoint = <&isp0_vir1>; }; }; }; &rkcif_mipi_lvds3 { status = "okay"; port { cif_mipi_in3: endpoint { remote-endpoint = <&mipi3_csi2_output>; }; }; }; &rkcif_mipi_lvds3_sditf { status = "okay"; port { mipi3_lvds_sditf: endpoint { remote-endpoint = <&isp1_vir1>; }; }; }; &rkcif_mipi_lvds4 { status = "okay"; port { cif_mipi_in4: endpoint { remote-endpoint = <&mipi4_csi2_output>; }; }; }; &rkcif_mipi_lvds4_sditf { status = "okay"; port { mipi4_lvds_sditf: endpoint { remote-endpoint = <&isp0_vir2>; }; }; }; &rkcif_mipi_lvds5 { status = "okay"; port { cif_mipi_in5: endpoint { remote-endpoint = <&mipi5_csi2_output>; }; }; }; &rkcif_mipi_lvds5_sditf { status = "okay"; port { mipi5_lvds_sditf: endpoint { remote-endpoint = <&isp1_vir2>; }; }; }; &rkcif_mmu { status = "okay"; }; &rkisp0 { status = "okay"; }; &isp0_mmu { status = "okay"; }; &rkisp0_vir0 { status = "okay"; port { #address-cells = <1>; #size-cells = <0>; isp0_vir0: endpoint@0 { reg = <0>; remote-endpoint = <&mipi_lvds_sditf>; }; }; }; &rkisp0_vir1 { status = "okay"; port { #address-cells = <1>; #size-cells = <0>; isp0_vir1: endpoint@0 { reg = <0>; remote-endpoint = <&mipi2_lvds_sditf>; }; }; }; &rkisp0_vir2 { status = "okay"; port { #address-cells = <1>; #size-cells = <0>; isp0_vir2: endpoint@0 { reg = <0>; remote-endpoint = <&mipi4_lvds_sditf>; }; }; }; &rkisp1 { status = "okay"; }; &isp1_mmu { status = "okay"; }; &rkisp1_vir0 { status = "okay"; port { #address-cells = <1>; #size-cells = <0>; isp1_vir0: endpoint@0 { reg = <0>; remote-endpoint = <&mipi1_lvds_sditf>; }; }; }; &rkisp1_vir1 { status = "okay"; port { #address-cells = <1>; #size-cells = <0>; isp1_vir1: endpoint@0 { reg = <0>; remote-endpoint = <&mipi3_lvds_sditf>; }; }; }; &rkisp1_vir2 { status = "okay"; port { #address-cells = <1>; #size-cells = <0>; isp1_vir2: endpoint@0 { reg = <0>; remote-endpoint = <&mipi5_lvds_sditf>; }; }; };