// SPDX-License-Identifier: GPL-2.0 ///***************************************** // Copyright (C) 2009-2019 // ITE Tech. Inc. All Rights Reserved ///***************************************** // @file // @author Jau-Chih.Tseng@ite.com.tw // @date 2019/02/15 // @fileversion: IT6161_SAMPLE_0.50 //******************************************/ typedef enum _SYS_STATUS { ER_SUCCESS = 0, ER_FAIL, ER_RESERVED } SYS_STATUS ; //#define FALSE 0 //#define TRUE 1 #ifndef NULL #define NULL ((void *) 0) #endif struct register_load_table { unsigned char offset; unsigned char mask; unsigned char value; }; /////////////////////////////////////////////////////////////////////// // Video Data Type /////////////////////////////////////////////////////////////////////// #define F_MODE_RGB444 0 #define F_MODE_YUV422 1 #define F_MODE_YUV444 2 #define F_MODE_CLRMOD_MASK 3 #define F_MODE_INTERLACE 1 #define F_VIDMODE_ITU709 (1<<4) #define F_VIDMODE_ITU601 0 #define F_VIDMODE_0_255 0 #define F_VIDMODE_16_235 (1<<5) #define F_VIDMODE_EN_UDFILT (1<<6) #define F_VIDMODE_EN_DITHER (1<<7) #define T_MODE_CCIR656 (1<<0) #define T_MODE_SYNCEMB (1<<1) #define T_MODE_INDDR (1<<2) #define T_MODE_PCLKDIV2 (1<<3) #define T_MODE_DEGEN (1<<4) #define T_MODE_SYNCGEN (1<<5) ///////////////////////////////////////////////////////////////////// // Packet and Info Frame definition and datastructure. ///////////////////////////////////////////////////////////////////// #define VENDORSPEC_INFOFRAME_TYPE 0x81 #define AVI_INFOFRAME_TYPE 0x82 #define SPD_INFOFRAME_TYPE 0x83 #define AUDIO_INFOFRAME_TYPE 0x84 #define MPEG_INFOFRAME_TYPE 0x85 #define VENDORSPEC_INFOFRAME_VER 0x01 #define AVI_INFOFRAME_VER 0x02 #define SPD_INFOFRAME_VER 0x01 #define AUDIO_INFOFRAME_VER 0x01 #define MPEG_INFOFRAME_VER 0x01 #define VENDORSPEC_INFOFRAME_LEN 5 #define AVI_INFOFRAME_LEN 13 #define SPD_INFOFRAME_LEN 25 #define AUDIO_INFOFRAME_LEN 10 #define MPEG_INFOFRAME_LEN 10 #define ACP_PKT_LEN 9 #define ISRC1_PKT_LEN 16 #define ISRC2_PKT_LEN 16 typedef union _VendorSpecific_InfoFrame { struct { u8 Type ; u8 Ver ; u8 Len ; u8 CheckSum; u8 IEEE_0;//PB1 u8 IEEE_1;//PB2 u8 IEEE_2;//PB3 u8 Rsvd:5 ;//PB4 u8 HDMI_Video_Format:3 ; u8 Reserved_PB5:4 ;//PB5 u8 _3D_Structure:4 ; u8 Reserved_PB6:4 ;//PB6 u8 _3D_Ext_Data:4 ; } info ; struct { u8 VS_HB[3] ; u8 CheckSum; u8 VS_DB[28] ; } pktbyte ; } VendorSpecific_InfoFrame ; typedef union _AVI_InfoFrame { struct { u8 Type; u8 Ver; u8 Len; u8 checksum ; u8 Scan:2; u8 BarInfo:2; u8 ActiveFmtInfoPresent:1; u8 ColorMode:2; u8 FU1:1; u8 ActiveFormatAspectRatio:4; u8 PictureAspectRatio:2; u8 Colorimetry:2; u8 Scaling:2; u8 FU2:6; u8 VIC:7; u8 FU3:1; u8 PixelRepetition:4; u8 FU4:4; u16 Ln_End_Top; u16 Ln_Start_Bottom; u16 Pix_End_Left; u16 Pix_Start_Right; } info; struct { u8 AVI_HB[3]; u8 checksum ; u8 AVI_DB[AVI_INFOFRAME_LEN]; } pktbyte; } AVI_InfoFrame; typedef union _Audio_InfoFrame { struct { u8 Type; u8 Ver; u8 Len; u8 checksum ; u8 AudioChannelCount:3; u8 RSVD1:1; u8 AudioCodingType:4; u8 SampleSize:2; u8 SampleFreq:3; u8 Rsvd2:3; u8 FmtCoding; u8 SpeakerPlacement; u8 Rsvd3:3; u8 LevelShiftValue:4; u8 DM_INH:1; } info; struct { u8 AUD_HB[3]; u8 checksum ; u8 AUD_DB[10]; } pktbyte; } Audio_InfoFrame; typedef union _MPEG_InfoFrame { struct { u8 Type; u8 Ver; u8 Len; u8 checksum ; u32 MpegBitRate; u8 MpegFrame:2; u8 Rvsd1:2; u8 FieldRepeat:1; u8 Rvsd2:3; } info; struct { u8 MPG_HB[3]; u8 checksum ; u8 MPG_DB[MPEG_INFOFRAME_LEN]; } pktbyte; } MPEG_InfoFrame; typedef union _SPD_InfoFrame { struct { u8 Type; u8 Ver; u8 Len; u8 checksum ; char VN[8]; char PD[16]; u8 SourceDeviceInfomation; } info; struct { u8 SPD_HB[3]; u8 checksum ; u8 SPD_DB[SPD_INFOFRAME_LEN]; } pktbyte; } SPD_InfoFrame; /////////////////////////////////////////////////////////////////////////// // Using for interface. /////////////////////////////////////////////////////////////////////////// #define PROG 1 #define INTERLACE 0 #define Vneg 0 #define Hneg 0 #define Vpos 1 #define Hpos 1 typedef struct { u32 H_ActiveStart; u32 H_ActiveEnd; u32 H_SyncStart; u32 H_SyncEnd; u32 V_ActiveStart; u32 V_ActiveEnd; u32 V_SyncStart; u32 V_SyncEnd; u32 V2_ActiveStart; u32 V2_ActiveEnd; u32 HTotal; u32 VTotal; } CEAVTiming; typedef struct { u8 VIC ; u8 PixelRep ; u32 HActive; u32 VActive; u32 HTotal; u32 VTotal; u32 PCLK; u16 xCnt; u32 HFrontPorch; u32 HSyncWidth; u32 HBackPorch; u8 VFrontPorch; u8 VSyncWidth; u8 VBackPorch; u8 ScanMode:1; u8 VPolarity:1; u8 HPolarity:1; } HDMI_VTiming; ////////////////////////////////////////////////////////////////// // Audio relate definition and macro. ////////////////////////////////////////////////////////////////// // 2008/08/15 added by jj_tseng@chipadvanced #define F_AUDIO_ON (1<<7) #define F_AUDIO_HBR (1<<6) #define F_AUDIO_DSD (1<<5) #define F_AUDIO_NLPCM (1<<4) #define F_AUDIO_LAYOUT_1 (1<<3) #define F_AUDIO_LAYOUT_0 (0<<3) // HBR - 1100 // DSD - 1010 // NLPCM - 1001 // LPCM - 1000 #define T_AUDIO_MASK 0xF0 #define T_AUDIO_OFF 0 #define T_AUDIO_HBR (F_AUDIO_ON|F_AUDIO_HBR) #define T_AUDIO_DSD (F_AUDIO_ON|F_AUDIO_DSD) #define T_AUDIO_NLPCM (F_AUDIO_ON|F_AUDIO_NLPCM) #define T_AUDIO_LPCM (F_AUDIO_ON) // for sample clock #define AUDFS_22p05KHz 4 #define AUDFS_44p1KHz 0 #define AUDFS_88p2KHz 8 #define AUDFS_176p4KHz 12 #define AUDFS_24KHz 6 #define AUDFS_48KHz 2 #define AUDFS_96KHz 10 #define AUDFS_192KHz 14 #define AUDFS_768KHz 9 #define AUDFS_32KHz 3 #define AUDFS_OTHER 1 // Audio Enable #define ENABLE_SPDIF (1<<4) #define ENABLE_I2S_SRC3 (1<<3) #define ENABLE_I2S_SRC2 (1<<2) #define ENABLE_I2S_SRC1 (1<<1) #define ENABLE_I2S_SRC0 (1<<0) #define AUD_SWL_NOINDICATE 0x0 #define AUD_SWL_16 0x2 #define AUD_SWL_17 0xC #define AUD_SWL_18 0x4 #define AUD_SWL_20 0xA // for maximum 20 bit #define AUD_SWL_21 0xD #define AUD_SWL_22 0x5 #define AUD_SWL_23 0x9 #define AUD_SWL_24 0xB #ifndef _IT6161_CONFIG_H_ #define _IT6161_CONFIG_H_ #define IC_VERSION (0xC0) #if (IC_VERSION == 0xC0) #pragma message("Defined IC_VERSION C0") #endif // EXTERN_HDCPROM /*************************************************************************************************/ //HDMITX /*************************************************************************************************/ #pragma message("config.h") #ifdef EXTERN_HDCPROM #pragma message("Defined EXTERN_HDCPROM") #endif // EXTERN_HDCPROM #define SUPPORT_EDID #define SUPPORT_HDCP #define SUPPORT_SHA //#define SUPPORT_AUDIO_MONITOR #define AudioOutDelayCnt 250 // #define SUPPORT_CEC ////////////////////////////////////////////////////////////////////////////////////////// // Video Configuration ////////////////////////////////////////////////////////////////////////////////////////// // 2010/01/26 added a option to disable HDCP. #define SUPPORT_OUTPUTYUV #define SUPPORT_OUTPUTRGB // #define DISABLE_HDMITX_CSC #define SUPPORT_INPUTRGB #define SUPPORT_INPUTYUV444 #define SUPPORT_INPUTYUV422 // #define SUPPORT_SYNCEMBEDDED // #define SUPPORT_DEGEN #define NON_SEQUENTIAL_YCBCR422 #define INPUT_COLOR_MODE F_MODE_RGB444 //#define INPUT_COLOR_MODE F_MODE_YUV422 //#define INPUT_COLOR_MODE F_MODE_YUV444 #define INPUT_COLOR_DEPTH 24 // #define INPUT_COLOR_DEPTH 30 // #define INPUT_COLOR_DEPTH 36 //#define OUTPUT_3D_MODE Frame_Pcaking //#define OUTPUT_3D_MODE Top_and_Botton //#define OUTPUT_3D_MODE Side_by_Side // #define INV_INPUT_ACLK // #define INV_INPUT_PCLK #ifdef USING_IT66120 #pragma message("Defined Using IT66120") #define SUPPORT_SYNCEMBEDDED #endif #ifdef SUPPORT_SYNCEMBEDDED #ifndef USING_IT66120 // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB) // 16 bit sync embedded // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB | T_MODE_CCIR656) // 8 bit sync embedded #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR|T_MODE_PCLKDIV2) // 16 bit sync embedded DDR // #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB|T_MODE_INDDR) // 8 bit sync embedded DDR #else #define INPUT_SIGNAL_TYPE (T_MODE_SYNCEMB | T_MODE_CCIR656) // 8 bit sync embedded #endif #define SUPPORT_INPUTYUV422 #ifdef INPUT_COLOR_MODE #undef INPUT_COLOR_MODE #endif // INPUT_COLOR_MODE #define INPUT_COLOR_MODE F_MODE_YUV422 #else #pragma message ("Defined seperated sync.") #define INPUT_SIGNAL_TYPE 0 // 24 bit sync seperate //#define INPUT_SIGNAL_TYPE ( T_MODE_DEGEN ) //#define INPUT_SIGNAL_TYPE ( T_MODE_INDDR) //#define INPUT_SIGNAL_TYPE ( T_MODE_SYNCEMB) //#define INPUT_SIGNAL_TYPE ( T_MODE_CCIR656 | T_MODE_SYNCEMB ) #endif #if defined(SUPPORT_INPUTYUV444) || defined(SUPPORT_INPUTYUV422) #define SUPPORT_INPUTYUV #endif #ifdef SUPPORT_SYNCEMBEDDED #pragma message("defined SUPPORT_SYNCEMBEDDED for Sync Embedded timing input or CCIR656 input.") #endif ////////////////////////////////////////////////////////////////////////////////////////// // Audio Configuration ////////////////////////////////////////////////////////////////////////////////////////// // #define SUPPORT_HBR_AUDIO #define USE_SPDIF_CHSTAT #ifndef SUPPORT_HBR_AUDIO #define INPUT_SAMPLE_FREQ AUDFS_48KHz #define INPUT_SAMPLE_FREQ_HZ 48000L #define OUTPUT_CHANNEL 2 // 3 // 4 // 5//6 //7 //8 #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_LPCM // #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_NLPCM #define CONFIG_INPUT_AUDIO_INTERFACE I2S // #define CONFIG_INPUT_AUDIO_INTERFACE SPDIF // #define CONFIG_INPUT_AUDIO_INTERFACE TDM // #define I2S_FORMAT 0x00 // 24bit I2S audio #define I2S_FORMAT 0x01 // 32bit I2S audio // #define I2S_FORMAT 0x02 // 24bit I2S audio, right justify // #define I2S_FORMAT 0x03 // 32bit I2S audio, right justify #else // SUPPORT_HBR_AUDIO #define INPUT_SAMPLE_FREQ AUDFS_768KHz #define INPUT_SAMPLE_FREQ_HZ 768000L #define OUTPUT_CHANNEL 8 #define CNOFIG_INPUT_AUDIO_TYPE T_AUDIO_HBR #define CONFIG_INPUT_AUDIO_INTERFACE FALSE // I2S // #define CONFIG_INPUT_AUDIO_INTERFACE TRUE // SPDIF #define I2S_FORMAT 0x47 // 32bit audio #endif ////////////////////////////////////////////////////////////////////////////////////////// // Audio Monitor Configuration ////////////////////////////////////////////////////////////////////////////////////////// //#define HDMITX_AUTO_MONITOR_INPUT #define HDMITX_INPUT_INFO #ifdef HDMITX_AUTO_MONITOR_INPUT #define HDMITX_INPUT_INFO #endif ////////////////////////////////////////////////////////////////////////////////////////// // Reduce Source Clock Jitter ////////////////////////////////////////////////////////////////////////////////////////// //#define REDUCE_HDMITX_SRC_JITTER ////////////////////////////////////////////////////////////////////////////////////////// // MIPI Rx Configuration ////////////////////////////////////////////////////////////////////////////////////////// #define MIPIRX_LANE_NUM 4 //1~4 #endif #ifndef _HDMITX_H_ #define _HDMITX_H_ #define HDMITX_MAX_DEV_COUNT 1 /////////////////////////////////////////////////////////////////////// // Output Mode Type /////////////////////////////////////////////////////////////////////// #define RES_ASPEC_4x3 0 #define RES_ASPEC_16x9 1 #define F_MODE_REPT_NO 0 #define F_MODE_REPT_TWICE 1 #define F_MODE_REPT_QUATRO 3 #define F_MODE_CSC_ITU601 0 #define F_MODE_CSC_ITU709 1 #define TIMER_LOOP_LEN 10 #define MS(x) (((x)+(TIMER_LOOP_LEN-1))/TIMER_LOOP_LEN); // for timer loop // #define SUPPORT_AUDI_AudSWL 16 // Jeilin case. #define SUPPORT_AUDI_AudSWL 24 // Jeilin case. #if(SUPPORT_AUDI_AudSWL==16) #define CHTSTS_SWCODE 0x02 #elif(SUPPORT_AUDI_AudSWL==18) #define CHTSTS_SWCODE 0x04 #elif(SUPPORT_AUDI_AudSWL==20) #define CHTSTS_SWCODE 0x03 #else #define CHTSTS_SWCODE 0x0B #endif #endif // _HDMITX_H_ ///***************************************** // Copyright (C) 2009-2019 // ITE Tech. Inc. All Rights Reserved // Proprietary and Confidential ///***************************************** // @file // @author Jau-Chih.Tseng@ite.com.tw // @date 2019/02/15 // @fileversion: IT6161_SAMPLE_0.50 //******************************************/ #ifndef _HDMITX_DRV_H_ #define _HDMITX_DRV_H_ //#define EXTERN_HDCPROM ///////////////////////////////////////// // DDC Address ///////////////////////////////////////// #define DDC_HDCP_ADDRESS 0x74 #define DDC_EDID_ADDRESS 0xA0 #define DDC_FIFO_MAXREQ 0x20 // I2C address #define _80MHz 80000000 #define HDMI_TX_I2C_SLAVE_ADDR 0x98 #define CEC_I2C_SLAVE_ADDR 0x9C /////////////////////////////////////////////////////////////////////// // Register offset /////////////////////////////////////////////////////////////////////// #define REG_TX_VENDOR_ID0 0x00 #define REG_TX_VENDOR_ID1 0x01 #define REG_TX_DEVICE_ID0 0x02 #define REG_TX_DEVICE_ID1 0x03 #define O_TX_DEVID 0 #define M_TX_DEVID 0xF #define O_TX_REVID 4 #define M_TX_REVID 0xF #define REG_TX_SW_RST 0x04 #define B_TX_ENTEST (1<<7) #define B_TX_REF_RST_HDMITX (1<<5) #define B_TX_AREF_RST (1<<4) #define B_HDMITX_VID_RST (1<<3) #define B_HDMITX_AUD_RST (1<<2) #define B_TX_HDMI_RST (1<<1) #define B_TX_HDCP_RST_HDMITX (1<<0) #define REG_TX_INT_CTRL 0x05 #define B_TX_INTPOL_ACTL 0 #define B_TX_INTPOL_ACTH (1<<7) #define B_TX_INT_PUSHPULL 0 #define B_TX_INT_OPENDRAIN (1<<6) #define REG_TX_INT_STAT1 0x06 #define B_TX_INT_AUD_OVERFLOW (1<<7) #define B_TX_INT_ROMACQ_NOACK (1<<6) #define B_TX_INT_RDDC_NOACK (1<<5) #define B_TX_INT_DDCFIFO_ERR (1<<4) #define B_TX_INT_ROMACQ_BUS_HANG (1<<3) #define B_TX_INT_DDC_BUS_HANG (1<<2) #define B_TX_INT_RX_SENSE (1<<1) #define B_TX_INT_HPD_PLUG (1<<0) #define REG_TX_INT_STAT2 0x07 #define B_TX_INT_HDCP_SYNC_DET_FAIL (1<<7) #define B_TX_INT_VID_UNSTABLE (1<<6) #define B_TX_INT_PKTACP (1<<5) #define B_TX_INT_PKTNULL (1<<4) #define B_TX_INT_PKTGENERAL (1<<3) #define B_TX_INT_KSVLIST_CHK (1<<2) #define B_TX_INT_AUTH_DONE (1<<1) #define B_TX_INT_AUTH_FAIL (1<<0) #define REG_TX_INT_STAT3 0x08 #define B_TX_INT_AUD_CTS (1<<6) #define B_TX_INT_VSYNC (1<<5) #define B_TX_INT_VIDSTABLE (1<<4) #define B_TX_INT_PKTMPG (1<<3) #define B_TX_INT_PKTSPD (1<<2) #define B_TX_INT_PKTAUD (1<<1) #define B_TX_INT_PKTAVI (1<<0) #define REG_TX_INT_MASK1 0x09 #define B_TX_AUDIO_OVFLW_MASK (1<<7) #define B_TX_DDC_NOACK_MASK (1<<5) #define B_TX_DDC_FIFO_ERR_MASK (1<<4) #define B_TX_DDC_BUS_HANG_MASK (1<<2) #define B_TX_RXSEN_MASK (1<<1) #define B_TX_HPD_MASK (1<<0) #define REG_TX_INT_MASK2 0x0A #define B_TX_PKT_AVI_MASK (1<<7) #define B_TX_PKT_VID_UNSTABLE_MASK (1<<6) #define B_TX_PKT_ACP_MASK (1<<5) #define B_TX_PKT_NULL_MASK (1<<4) #define B_TX_PKT_GEN_MASK (1<<3) #define B_TX_KSVLISTCHK_MASK (1<<2) #define B_TX_AUTH_DONE_MASK (1<<1) #define B_TX_AUTH_FAIL_MASK (1<<0) #define REG_TX_INT_MASK3 0x0B #define B_TX_HDCP_SYNC_DET_FAIL_MASK (1<<6) #define B_TX_AUDCTS_MASK (1<<5) #define B_TX_VSYNC_MASK (1<<4) #define B_TX_VIDSTABLE_MASK (1<<3) #define B_TX_PKT_MPG_MASK (1<<2) #define B_TX_PKT_SPD_MASK (1<<1) #define B_TX_PKT_AUD_MASK (1<<0) #define REG_TX_INT_CLR0 0x0C #define B_TX_CLR_PKTACP (1<<7) #define B_TX_CLR_PKTNULL (1<<6) #define B_TX_CLR_PKTGENERAL (1<<5) #define B_TX_CLR_KSVLISTCHK (1<<4) #define B_TX_CLR_AUTH_DONE (1<<3) #define B_TX_CLR_AUTH_FAIL (1<<2) #define B_TX_CLR_RXSENSE (1<<1) #define B_TX_CLR_HPD (1<<0) #define REG_TX_INT_CLR1 0x0D #define B_TX_CLR_VSYNC (1<<7) #define B_TX_CLR_VIDSTABLE (1<<6) #define B_TX_CLR_PKTMPG (1<<5) #define B_TX_CLR_PKTSPD (1<<4) #define B_TX_CLR_PKTAUD (1<<3) #define B_TX_CLR_PKTAVI (1<<2) #define B_TX_CLR_HDCP_SYNC_DET_FAIL (1<<1) #define B_TX_CLR_VID_UNSTABLE (1<<0) #define REG_TX_SYS_STATUS 0x0E // readonly #define B_TX_INT_ACTIVE (1<<7) #define B_TX_HPDETECT (1<<6) #define B_TX_RXSENDETECT (1<<5) #define B_TXVIDSTABLE (1<<4) // read/write #define O_TX_CTSINTSTEP 2 #define M_TX_CTSINTSTEP (3<<2) #define B_TX_CLR_AUD_CTS (1<<1) #define B_TX_INTACTDONE (1<<0) #define REG_TX_BANK_CTRL 0x0F #define B_TX_BANK0 0 #define B_TX_BANK1 1 // DDC #define REG_TX_DDC_MASTER_CTRL 0x10 #define B_TX_MASTERROM (1<<1) #define B_TX_MASTERDDC (0<<1) #define B_TX_MASTERHOST (1<<0) #define B_TX_MASTERHDCP (0<<0) #define REG_TX_DDC_HEADER 0x11 #define REG_TX_DDC_REQOFF 0x12 #define REG_TX_DDC_REQCOUNT 0x13 #define REG_TX_DDC_EDIDSEG 0x14 #define REG_TX_DDC_CMD 0x15 #define CMD_DDC_SEQ_BURSTREAD 0 #define CMD_LINK_CHKREAD 2 #define CMD_EDID_READ 3 #define CMD_FIFO_CLR 9 #define CMD_GEN_SCLCLK 0xA #define CMD_DDC_ABORT 0xF #define REG_TX_DDC_STATUS 0x16 #define B_TX_DDC_DONE (1<<7) #define B_TX_DDC_ACT (1<<6) #define B_TX_DDC_NOACK (1<<5) #define B_TX_DDC_WAITBUS (1<<4) #define B_TX_DDC_ARBILOSE (1<<3) #define B_TX_DDC_ERROR (B_TX_DDC_NOACK|B_TX_DDC_WAITBUS|B_TX_DDC_ARBILOSE) #define B_TX_DDC_FIFOFULL (1<<2) #define B_TX_DDC_FIFOEMPTY (1<<1) #define REG_TX_DDC_READFIFO 0x17 #define REG_TX_ROM_STARTADDR 0x18 #define REG_TX_HDCP_HEADER 0x19 #define REG_TX_ROM_HEADER 0x1A #define REG_TX_BUSHOLD_T 0x1B #define REG_TX_ROM_STAT 0x1C #define B_TX_ROM_DONE (1<<7) #define B_TX_ROM_ACTIVE (1<<6) #define B_TX_ROM_NOACK (1<<5) #define B_TX_ROM_WAITBUS (1<<4) #define B_TX_ROM_ARBILOSE (1<<3) #define B_TX_ROM_BUSHANG (1<<2) // HDCP #define REG_TX_AN_GENERATE 0x1F #define B_TX_START_CIPHER_GEN 1 #define B_TX_STOP_CIPHER_GEN 0 #define REG_TX_CLK_CTRL0 0x58 #define O_TX_OSCLK_SEL 5 #define M_TX_OSCLK_SEL 3 #define B_TX_AUTO_OVER_SAMPLING_CLOCK (1<<4) #define O_TX_EXT_MCLK_SEL 2 #define M_TX_EXT_MCLK_SEL (3<