144 lines
4.3 KiB
ArmAsm
144 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <drivers/arm/fvp/fvp_pwrc.h>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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.globl plat_arm_calc_core_pos
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/* --------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* For AArch32, cold-booting secondary CPUs is not yet
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* implemented and they panic.
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot. On FVP, this information can be queried from the power
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* controller. The Power Control SYS Status Register (PSYSR) indicates
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* the wake-up reason for the CPU.
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*
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* For a cold boot, return 0.
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* ---------------------------------------------------------------------
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* When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
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* WakeRequest signal" then it is a warm boot.
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* ---------------------------------------------------------------------
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*/
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ldcopr r2, MPIDR
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ldr r1, =PWRC_BASE
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str r2, [r1, #PSYSR_OFF]
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ldr r2, [r1, #PSYSR_OFF]
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ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
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cmp r2, #WKUP_PPONR
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beq warm_reset
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cmp r2, #WKUP_GICREQ
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beq warm_reset
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/* Cold reset */
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mov r0, #0
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bx lr
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warm_reset:
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/* ---------------------------------------------------------------------
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* A mailbox is maintained in the trusted SRAM. It is flushed out of the
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* caches after every update using normal memory so it is safe to read
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* it here with SO attributes.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr r0, [r0]
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cmp r0, #0
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beq _panic
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bx lr
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/* ---------------------------------------------------------------------
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* The power controller indicates this is a warm reset but the mailbox
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* is empty. This should never happen!
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* ---------------------------------------------------------------------
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*/
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_panic:
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b _panic
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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ldcopr r0, MPIDR
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ldr r1, =MPIDR_AFFINITY_MASK
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and r0, r1
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cmp r0, #FVP_PRIMARY_CPU
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moveq r0, #1
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movne r0, #0
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bx lr
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endfunc plat_is_my_cpu_primary
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/* ---------------------------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Function to calculate the core position on FVP.
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*
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* (ClusterId * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) +
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* (CPUId * FVP_MAX_PE_PER_CPU) +
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* ThreadId
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*
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* which can be simplified as:
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*
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* ((ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU)
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* + ThreadId
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* ---------------------------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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mov r3, r0
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/*
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* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
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* look as if in a multi-threaded implementation
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*/
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tst r0, #MPIDR_MT_MASK
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lsleq r3, r0, #MPIDR_AFFINITY_BITS
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/* Extract individual affinity fields from MPIDR */
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ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov r3, #FVP_MAX_CPUS_PER_CLUSTER
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mla r1, r2, r3, r1
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mov r3, #FVP_MAX_PE_PER_CPU
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mla r0, r1, r3, r0
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bx lr
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endfunc plat_arm_calc_core_pos
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