145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <lib/optee_utils.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/rpi3/gpio/rpi3_gpio.h>
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#include <drivers/rpi3/sdhost/rpi3_sdhost.h>
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#include <rpi_shared.h>
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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/* Data structure which holds the MMC info */
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static struct mmc_device_info mmc_info;
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static void rpi3_sdhost_setup(void)
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{
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struct rpi3_sdhost_params params;
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memset(¶ms, 0, sizeof(struct rpi3_sdhost_params));
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params.reg_base = RPI3_SDHOST_BASE;
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params.bus_width = MMC_BUS_WIDTH_1;
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params.clk_rate = 50000000;
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mmc_info.mmc_dev_type = MMC_IS_SD_HC;
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rpi3_sdhost_init(¶ms, &mmc_info);
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}
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/*******************************************************************************
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* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
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* in x0. This memory layout is sitting at the base of the free trusted SRAM.
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* Copy it to a safe location before its reclaimed by later BL2 functionality.
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******************************************************************************/
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void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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meminfo_t *mem_layout = (meminfo_t *) arg1;
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/* Initialize the console to provide early debug support */
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rpi3_console_init();
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/* Enable arch timer */
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generic_delay_timer_init();
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/* Setup GPIO driver */
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rpi3_gpio_init();
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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/* Setup SDHost driver */
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rpi3_sdhost_setup();
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plat_rpi3_io_setup();
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}
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void bl2_platform_setup(void)
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{
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/*
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* This is where a TrustZone address space controller and other
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* security related peripherals would be configured.
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*/
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here.
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******************************************************************************/
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void bl2_plat_arch_setup(void)
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{
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rpi3_setup_page_tables(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL_CODE_BASE, BL_CODE_END,
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BL_RO_DATA_BASE, BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el1(0);
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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#ifdef SPD_opteed
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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#endif
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assert(bl_mem_params != NULL);
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switch (image_id) {
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case BL32_IMAGE_ID:
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#ifdef SPD_opteed
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0)
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WARN("OPTEE header parse error.\n");
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#endif
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bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry();
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break;
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case BL33_IMAGE_ID:
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
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/* Shutting down the SDHost driver to let BL33 drives SDHost.*/
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rpi3_sdhost_stop();
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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