222 lines
8.7 KiB
C
Executable File
222 lines
8.7 KiB
C
Executable File
/*
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* Broadcom USB remote download definitions
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*
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* Copyright (C) 2022, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _USB_RDL_H
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#define _USB_RDL_H
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/* Control messages: bRequest values */
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#define DL_GETSTATE 0 /* returns the rdl_state_t struct */
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#define DL_CHECK_CRC 1 /* currently unused */
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#define DL_GO 2 /* execute downloaded image */
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#define DL_START 3 /* initialize dl state */
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#define DL_REBOOT 4 /* reboot the device in 2 seconds */
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#define DL_GETVER 5 /* returns the bootrom_id_t struct */
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#define DL_GO_PROTECTED 6 /* execute the downloaded code and set reset event
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* to occur in 2 seconds. It is the responsibility
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* of the downloaded code to clear this event
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*/
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#define DL_EXEC 7 /* jump to a supplied address */
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#define DL_RESETCFG 8 /* To support single enum on dongle
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* - Not used by bootloader
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*/
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#define DL_DEFER_RESP_OK 9 /* Potentially defer the response to setup
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* if resp unavailable
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*/
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#define DL_CHGSPD 0x0A
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#define DL_HWCMD_MASK 0xfc /* Mask for hardware read commands: */
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#define DL_RDHW 0x10 /* Read a hardware address (Ctl-in) */
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#define DL_RDHW32 0x10 /* Read a 32 bit word */
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#define DL_RDHW16 0x11 /* Read 16 bits */
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#define DL_RDHW8 0x12 /* Read an 8 bit byte */
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#define DL_WRHW 0x14 /* Write a hardware address (Ctl-out) */
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#define DL_WRHW_BLK 0x13 /* Block write to hardware access */
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#define DL_CMD_WRHW 2 /* write data to a backplane address */
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#define DL_CMD_RDHW 1 /* read data from a backplane address */
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#define DL_JTCONF 0x15 /* Get JTAG configuration (Ctl_in)
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* Set JTAG configuration (Ctl-out)
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*/
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#define DL_JTON 0x16 /* Turn on jtag master (Ctl-in) */
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#define DL_JTOFF 0x17 /* Turn on jtag master (Ctl-in) */
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#define DL_RDRJT 0x18 /* Read a JTAG register (Ctl-in) */
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#define DL_WRJT 0x19 /* Write a hardware address over JTAG (Ctl/Bulk-out) */
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#define DL_WRRJT 0x1a /* Write a JTAG register (Ctl/Bulk-out) */
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#define DL_JTRST 0x1b /* Reset jtag fsm on jtag DUT (Ctl-in) */
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#define DL_RDJT 0x1c /* Read a hardware address over JTAG (Ctl-in) */
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#define DL_RDJT32 0x1c /* Read 32 bits */
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#define DL_RDJT16 0x1e /* Read 16 bits (sz = 4 - low bits) */
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#define DL_RDJT8 0x1f /* Read 8 bits */
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#define DL_MRDJT 0x20 /* Multiple read over JTAG (Ctl-out+Bulk-in) */
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#define DL_MRDJT32 0x20 /* M-read 32 bits */
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#define DL_MRDJT16 0x22 /* M-read 16 bits (sz = 4 - low bits) */
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#define DL_MRDJT6 0x23 /* M-read 8 bits */
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#define DL_MRDIJT 0x24 /* M-read over JTAG (Ctl-out+Bulk-in) with auto-increment */
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#define DL_MRDIJT32 0x24 /* M-read 32 bits w/ai */
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#define DL_MRDIJT16 0x26 /* M-read 16 bits w/ai (sz = 4 - low bits) */
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#define DL_MRDIJT8 0x27 /* M-read 8 bits w/ai */
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#define DL_MRDDJT 0x28 /* M-read over JTAG (Ctl-out+Bulk-in) with auto-decrement */
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#define DL_MRDDJT32 0x28 /* M-read 32 bits w/ad */
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#define DL_MRDDJT16 0x2a /* M-read 16 bits w/ad (sz = 4 - low bits) */
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#define DL_MRDDJT8 0x2b /* M-read 8 bits w/ad */
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#define DL_MWRJT 0x2c /* Multiple write over JTAG (Bulk-out) */
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#define DL_MWRIJT 0x2d /* With auto-increment */
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#define DL_MWRDJT 0x2e /* With auto-decrement */
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#define DL_VRDJT 0x2f /* Vector read over JTAG (Bulk-out+Bulk-in) */
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#define DL_VWRJT 0x30 /* Vector write over JTAG (Bulk-out+Bulk-in) */
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#define DL_SCJT 0x31 /* Jtag scan (Bulk-out+Bulk-in) */
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#define DL_CFRD 0x33 /* Reserved for dmamem use */
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#define DL_CFWR 0x34 /* Reserved for dmamem use */
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#define DL_GET_NVRAM 0x35 /* Query nvram parameter */
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#define DL_ENABLE_U1U2 0x36 /* Enable U1 and U2 */
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#define DL_DBGTRIG 0xFF /* Trigger bRequest type to aid debug */
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#define DL_JTERROR 0x80000000
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/* states */
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#define DL_WAITING 0 /* waiting to rx first pkt that includes the hdr info */
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#define DL_READY 1 /* hdr was good, waiting for more of the compressed image */
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#define DL_BAD_HDR 2 /* hdr was corrupted */
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#define DL_BAD_CRC 3 /* compressed image was corrupted */
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#define DL_RUNNABLE 4 /* download was successful, waiting for go cmd */
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#define DL_START_FAIL 5 /* failed to initialize correctly */
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#define DL_NVRAM_TOOBIG 6 /* host specified nvram data exceeds DL_NVRAM value */
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#define DL_IMAGE_TOOBIG 7 /* download image too big (exceeds DATA_START for rdl) */
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#define TIMEOUT 5000 /* Timeout for usb commands */
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struct bcm_device_id {
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char *name;
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uint32 vend;
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uint32 prod;
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};
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typedef struct {
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uint32 state;
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uint32 bytes;
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} rdl_state_t;
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typedef struct {
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uint32 chip; /* Chip id */
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uint32 chiprev; /* Chip rev */
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uint32 ramsize; /* Size of RAM */
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uint32 remapbase; /* Current remap base address */
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uint32 boardtype; /* Type of board */
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uint32 boardrev; /* Board revision */
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} bootrom_id_t;
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/* struct for backplane & jtag accesses */
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typedef struct {
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uint32 cmd; /* tag to identify the cmd */
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uint32 addr; /* backplane address for write */
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uint32 len; /* length of data: 1, 2, 4 bytes */
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uint32 data; /* data to write */
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} hwacc_t;
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/* struct for backplane */
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typedef struct {
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uint32 cmd; /* tag to identify the cmd */
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uint32 addr; /* backplane address for write */
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uint32 len; /* length of data: 1, 2, 4 bytes */
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uint8 data[BCM_FLEX_ARRAY]; /* data to write */
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} hwacc_blk_t;
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typedef struct {
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uint32 chip; /* Chip id */
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uint32 chiprev; /* Chip rev */
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uint32 ccrev; /* Chipcommon core rev */
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uint32 siclock; /* Backplane clock */
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} jtagd_id_t;
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/* Jtag configuration structure */
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typedef struct {
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uint32 cmd; /* tag to identify the cmd */
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uint8 clkd; /* Jtag clock divisor */
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uint8 disgpio; /* Gpio to disable external driver */
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uint8 irsz; /* IR size for readreg/writereg */
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uint8 drsz; /* DR size for readreg/writereg */
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uint8 bigend; /* Big endian */
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uint8 mode; /* Current mode */
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uint16 delay; /* Delay between jtagm "simple commands" */
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uint32 retries; /* Number of retries for jtagm operations */
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uint32 ctrl; /* Jtag control reg copy */
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uint32 ir_lvbase; /* Bits to add to IR values in LV tap */
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uint32 dretries; /* Number of retries for dma operations */
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} jtagconf_t;
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/* struct for jtag scan */
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#define MAX_USB_IR_BITS 256
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#define MAX_USB_DR_BITS 3072
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#define USB_IR_WORDS (MAX_USB_IR_BITS / 32)
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#define USB_DR_WORDS (MAX_USB_DR_BITS / 32)
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typedef struct {
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uint32 cmd; /* tag to identify the cmd */
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uint32 irsz; /* IR size in bits */
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uint32 drsz; /* DR size in bits */
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uint32 ts; /* Terminal state (def, pause, rti) */
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uint32 data[USB_IR_WORDS + USB_DR_WORDS]; /* IR & DR data */
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} scjt_t;
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/* struct for querying nvram params from bootloader */
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#define QUERY_STRING_MAX 32
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typedef struct {
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uint32 cmd; /* tag to identify the cmd */
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char var[QUERY_STRING_MAX]; /* param name */
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} nvparam_t;
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typedef void (*exec_fn_t)(void *sih);
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#define USB_CTRL_IN (USB_TYPE_VENDOR | 0x80 | USB_RECIP_INTERFACE)
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#define USB_CTRL_OUT (USB_TYPE_VENDOR | 0 | USB_RECIP_INTERFACE)
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#define USB_CTRL_EP_TIMEOUT 500 /* Timeout used in USB control_msg transactions. */
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#define USB_BULK_EP_TIMEOUT 500 /* Timeout used in USB bulk transactions. */
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#define RDL_CHUNK_MAX (64 * 1024) /* max size of each dl transfer */
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#define RDL_CHUNK 1500 /* size of each dl transfer */
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/* bootloader makes special use of trx header "offsets" array */
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#define TRX_OFFSETS_DLFWLEN_IDX 0 /* Size of the fw; used in uncompressed case */
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#define TRX_OFFSETS_JUMPTO_IDX 1 /* RAM address for jumpto after download */
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#define TRX_OFFSETS_NVM_LEN_IDX 2 /* Length of appended NVRAM data */
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#ifdef BCMTRXV2
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/* The NVRAM region part of trx will be digitally signed in SDR image,
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* so is the need for new cfg region which could pass parameters
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* which dones not need to be digitally signed
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*/
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#define TRX_OFFSETS_DSG_LEN_IDX 3 /* Length of digital signature for the first image */
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#define TRX_OFFSETS_CFG_LEN_IDX 4 /* Length of config region, which is not digitally signed */
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#endif /* BCMTRXV2 */
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#define TRX_OFFSETS_DLBASE_IDX 0 /* RAM start address for download */
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#endif /* _USB_RDL_H */
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