844 lines
20 KiB
C
844 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Motorcomm PHYs
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*
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* Author: Peter Geis <pgwipeout@gmail.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of_device.h>
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#include <linux/phy.h>
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#define PHY_ID_YT8511 0x0000010a
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#define PHY_ID_YT8512 0x00000118
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#define PHY_ID_YT8512B 0x00000128
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#define PHY_ID_YT8531S 0x4f51e91a
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#define PHY_ID_YT8531 0x4f51e91b
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#define YT8511_PAGE_SELECT 0x1e
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#define YT8511_PAGE 0x1f
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#define YT8511_EXT_CLK_GATE 0x0c
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#define YT8511_EXT_DELAY_DRIVE 0x0d
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#define YT8511_EXT_SLEEP_CTRL 0x27
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/* 2b00 25m from pll
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* 2b01 25m from xtl *default*
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* 2b10 62.m from pll
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* 2b11 125m from pll
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*/
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#define YT8511_CLK_125M (BIT(2) | BIT(1))
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#define YT8511_PLLON_SLP BIT(14)
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/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
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#define YT8511_DELAY_RX BIT(0)
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/* TX Gig-E Delay is bits 7:4, default 0x5
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* TX Fast-E Delay is bits 15:12, default 0xf
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* Delay = 150ps * N - 250ps
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* On = 2000ps, off = 50ps
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*/
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#define YT8511_DELAY_GE_TX_EN (0xf << 4)
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#define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
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#define YT8511_DELAY_FE_TX_EN (0xf << 12)
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#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
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#define YT8512_EXTREG_AFE_PLL 0x50
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#define YT8512_EXTREG_EXTEND_COMBO 0x4000
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#define YT8512_EXTREG_LED0 0x40c0
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#define YT8512_EXTREG_LED1 0x40c3
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#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
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#define YT_SOFTWARE_RESET 0x8000
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#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
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#define YT8512_CONTROL1_RMII_EN 0x0001
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#define YT8512_LED0_ACT_BLK_IND 0x1000
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#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
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#define YT8512_LED0_BT_BLK_EN 0x0002
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#define YT8512_LED0_HT_BLK_EN 0x0004
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#define YT8512_LED0_COL_BLK_EN 0x0008
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#define YT8512_LED0_BT_ON_EN 0x0010
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#define YT8512_LED1_BT_ON_EN 0x0010
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#define YT8512_LED1_TXACT_BLK_EN 0x0100
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#define YT8512_LED1_RXACT_BLK_EN 0x0200
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#define YT8512_SPEED_MODE 0xc000
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#define YT8512_DUPLEX 0x2000
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#define YT8512_SPEED_MODE_BIT 14
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#define YT8512_DUPLEX_BIT 13
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#define YT8512_EN_SLEEP_SW_BIT 15
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/* if system depends on ethernet packet to restore from sleep,
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* please define this macro to 1 otherwise, define it to 0.
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*/
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#define SYS_WAKEUP_BASED_ON_ETH_PKT 1
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/* to enable system WOL feature of phy, please define this macro to 1
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* otherwise, define it to 0.
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*/
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#define YTPHY_WOL_FEATURE_ENABLE 0
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#if (YTPHY_WOL_FEATURE_ENABLE)
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#undef SYS_WAKEUP_BASED_ON_ETH_PKT
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#define SYS_WAKEUP_BASED_ON_ETH_PKT 1
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#endif
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/* for YT8531 package A xtal init config */
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#define YTPHY8531A_XTAL_INIT 0
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#define REG_PHY_SPEC_STATUS 0x11
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#define REG_DEBUG_ADDR_OFFSET 0x1e
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#define REG_DEBUG_DATA 0x1f
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#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
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#define YT8521_EN_SLEEP_SW_BIT 15
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#define YT8521_SPEED_MODE 0xc000
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#define YT8521_DUPLEX 0x2000
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#define YT8521_SPEED_MODE_BIT 14
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#define YT8521_DUPLEX_BIT 13
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#define YT8521_LINK_STATUS_BIT 10
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/* YT8521 polling mode */
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#define YT8521_PHY_MODE_FIBER 1 /* fiber mode only */
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#define YT8521_PHY_MODE_UTP 2 /* utp mode only */
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#define YT8521_PHY_MODE_POLL 3 /* fiber and utp, poll mode */
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static int yt8521_hw_strap_polling(struct phy_device *phydev);
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#define YT8521_PHY_MODE_CURR yt8521_hw_strap_polling(phydev)
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static int yt8511_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, YT8511_PAGE_SELECT);
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};
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static int yt8511_write_page(struct phy_device *phydev, int page)
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{
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return __phy_write(phydev, YT8511_PAGE_SELECT, page);
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};
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static int yt8511_config_init(struct phy_device *phydev)
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{
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int oldpage, ret = 0;
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unsigned int ge, fe;
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oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
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if (oldpage < 0)
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goto err_restore_page;
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/* set rgmii delay mode */
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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ge = YT8511_DELAY_GE_TX_DIS;
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fe = YT8511_DELAY_FE_TX_DIS;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
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fe = YT8511_DELAY_FE_TX_DIS;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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ge = YT8511_DELAY_GE_TX_EN;
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fe = YT8511_DELAY_FE_TX_EN;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
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fe = YT8511_DELAY_FE_TX_EN;
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break;
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default: /* do not support other modes */
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ret = -EOPNOTSUPP;
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goto err_restore_page;
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}
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ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
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if (ret < 0)
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goto err_restore_page;
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/* set clock mode to 125mhz */
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ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
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if (ret < 0)
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goto err_restore_page;
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/* fast ethernet delay is in a separate page */
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ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
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if (ret < 0)
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goto err_restore_page;
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ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
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if (ret < 0)
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goto err_restore_page;
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/* leave pll enabled in sleep */
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ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
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if (ret < 0)
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goto err_restore_page;
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ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
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if (ret < 0)
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goto err_restore_page;
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err_restore_page:
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return phy_restore_page(phydev, oldpage, ret);
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}
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static u32 ytphy_read_ext(struct phy_device *phydev, u32 regnum)
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{
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int ret;
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phy_lock_mdio_bus(phydev);
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ret = __phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
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if (ret < 0)
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goto err_handle;
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ret = __phy_read(phydev, REG_DEBUG_DATA);
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if (ret < 0)
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goto err_handle;
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err_handle:
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phy_unlock_mdio_bus(phydev);
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return ret;
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}
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static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
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{
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int ret;
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phy_lock_mdio_bus(phydev);
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ret = __phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
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if (ret < 0)
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goto err_handle;
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ret = __phy_write(phydev, REG_DEBUG_DATA, val);
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if (ret < 0)
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goto err_handle;
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err_handle:
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phy_unlock_mdio_bus(phydev);
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return ret;
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}
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static int ytphy_soft_reset(struct phy_device *phydev)
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{
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int ret = 0, val = 0;
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val = phy_read(phydev, MII_BMCR);
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if (val < 0)
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return val;
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ret = phy_write(phydev, MII_BMCR, val | BMCR_RESET);
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if (ret < 0)
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return ret;
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return ret;
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}
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static int yt8512_clk_init(struct phy_device *phydev)
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{
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struct device_node *node = phydev->mdio.dev.of_node;
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const char *strings = NULL;
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int ret;
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int val;
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if (node && node->parent && node->parent->parent) {
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ret = of_property_read_string(node->parent->parent,
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"clock_in_out", &strings);
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if (!ret) {
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if (!strcmp(strings, "input"))
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return 0;
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}
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}
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val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
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if (val < 0)
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return val;
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val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
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if (ret < 0)
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return ret;
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val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
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if (val < 0)
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return val;
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val |= YT8512_CONTROL1_RMII_EN;
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
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if (ret < 0)
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return ret;
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val = phy_read(phydev, MII_BMCR);
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if (val < 0)
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return val;
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val |= YT_SOFTWARE_RESET;
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ret = phy_write(phydev, MII_BMCR, val);
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return ret;
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}
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static int yt8512_led_init(struct phy_device *phydev)
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{
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int ret;
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int val;
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int mask;
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val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
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if (val < 0)
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return val;
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val |= YT8512_LED0_ACT_BLK_IND;
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mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
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YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
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YT8512_LED0_BT_ON_EN;
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val &= ~mask;
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
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if (ret < 0)
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return ret;
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val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
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if (val < 0)
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return val;
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val |= YT8512_LED1_BT_ON_EN;
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mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
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val &= ~mask;
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ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
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return ret;
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}
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static int yt8512_config_init(struct phy_device *phydev)
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{
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int ret;
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int val;
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ret = yt8512_clk_init(phydev);
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if (ret < 0)
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return ret;
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ret = yt8512_led_init(phydev);
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if (ret < 0)
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return ret;
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/* disable auto sleep */
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val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
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if (val < 0)
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return val;
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val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
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if (ret < 0)
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return ret;
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return ret;
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}
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static int yt8512_read_status(struct phy_device *phydev)
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{
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int ret;
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int val;
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int speed, speed_mode, duplex;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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val = phy_read(phydev, REG_PHY_SPEC_STATUS);
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if (val < 0)
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return val;
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duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
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speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
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switch (speed_mode) {
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case 0:
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speed = SPEED_10;
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break;
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case 1:
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speed = SPEED_100;
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break;
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case 2:
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case 3:
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default:
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speed = SPEED_UNKNOWN;
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break;
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}
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phydev->speed = speed;
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phydev->duplex = duplex;
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return 0;
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}
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static int yt8521_soft_reset(struct phy_device *phydev)
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{
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int ret = 0, val;
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if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_UTP) {
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ytphy_write_ext(phydev, 0xa000, 0);
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ret = ytphy_soft_reset(phydev);
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if (ret < 0)
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return ret;
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}
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if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_FIBER) {
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ytphy_write_ext(phydev, 0xa000, 2);
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ret = ytphy_soft_reset(phydev);
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if (ret < 0)
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return ret;
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ytphy_write_ext(phydev, 0xa000, 0);
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}
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if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_POLL) {
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val = ytphy_read_ext(phydev, 0xa001);
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ytphy_write_ext(phydev, 0xa001, (val & ~0x8000));
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ytphy_write_ext(phydev, 0xa000, 0);
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ret = ytphy_soft_reset(phydev);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int yt8521_hw_strap_polling(struct phy_device *phydev)
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{
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int val = 0;
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val = ytphy_read_ext(phydev, 0xa001) & 0x7;
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switch (val) {
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case 1:
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case 4:
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case 5:
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return YT8521_PHY_MODE_FIBER;
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case 2:
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case 6:
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case 7:
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return YT8521_PHY_MODE_POLL;
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case 3:
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case 0:
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default:
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return YT8521_PHY_MODE_UTP;
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}
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}
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static int yt8521_config_init(struct phy_device *phydev)
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{
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int ret, hw_strap_mode;
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int val;
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#if (YTPHY_WOL_FEATURE_ENABLE)
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struct ethtool_wolinfo wol;
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/* set phy wol enable */
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memset(&wol, 0x0, sizeof(struct ethtool_wolinfo));
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wol.wolopts |= WAKE_MAGIC;
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ytphy_wol_feature_set(phydev, &wol);
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#endif
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phydev->irq = PHY_POLL;
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/* NOTE: this function should not be called more than one for each chip. */
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hw_strap_mode = ytphy_read_ext(phydev, 0xa001) & 0x7;
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ytphy_write_ext(phydev, 0xa000, 0);
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/* disable auto sleep */
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val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
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if (val < 0)
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return val;
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val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
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ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
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if (ret < 0)
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return ret;
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/* enable RXC clock when no wire plug */
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val = ytphy_read_ext(phydev, 0xc);
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if (val < 0)
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return val;
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val &= ~(1 << 12);
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ret = ytphy_write_ext(phydev, 0xc, val);
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if (ret < 0)
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return ret;
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netdev_info(phydev->attached_dev, "%s done, phy addr: %d, strap mode = %d, polling mode = %d\n",
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__func__, phydev->mdio.addr, hw_strap_mode, yt8521_hw_strap_polling(phydev));
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return ret;
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}
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/* for fiber mode, there is no 10M speed mode and
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* this function is for this purpose.
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*/
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static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
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{
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int speed = SPEED_UNKNOWN;
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int speed_mode, duplex;
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if (is_utp)
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duplex = (val & YT8521_DUPLEX) >> YT8521_DUPLEX_BIT;
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else
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duplex = 1;
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speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
|
|
switch (speed_mode) {
|
|
case 0:
|
|
if (is_utp)
|
|
speed = SPEED_10;
|
|
break;
|
|
case 1:
|
|
speed = SPEED_100;
|
|
break;
|
|
case 2:
|
|
speed = SPEED_1000;
|
|
break;
|
|
case 3:
|
|
break;
|
|
default:
|
|
speed = SPEED_UNKNOWN;
|
|
break;
|
|
}
|
|
|
|
phydev->speed = speed;
|
|
phydev->duplex = duplex;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* for fiber mode, when speed is 100M, there is no definition for
|
|
* autonegotiation, and this function handles this case and return
|
|
* 1 per linux kernel's polling.
|
|
*/
|
|
static int yt8521_aneg_done(struct phy_device *phydev)
|
|
{
|
|
int link_fiber = 0, link_utp = 0;
|
|
|
|
/* reading Fiber */
|
|
ytphy_write_ext(phydev, 0xa000, 2);
|
|
link_fiber = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
|
|
|
|
/* reading UTP */
|
|
ytphy_write_ext(phydev, 0xa000, 0);
|
|
if (!link_fiber)
|
|
link_utp = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
|
|
|
|
netdev_info(phydev->attached_dev, "%s, phy addr: %d, link_fiber: %d, link_utp: %d\n",
|
|
__func__, phydev->mdio.addr, link_fiber, link_utp);
|
|
return !!(link_fiber | link_utp);
|
|
}
|
|
|
|
static int yt8521_read_status(struct phy_device *phydev)
|
|
{
|
|
int link_utp = 0, link_fiber = 0;
|
|
int yt8521_fiber_latch_val;
|
|
int yt8521_fiber_curr_val;
|
|
int link, ret;
|
|
int val;
|
|
|
|
if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
|
|
/* reading UTP */
|
|
ret = ytphy_write_ext(phydev, 0xa000, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
val = phy_read(phydev, REG_PHY_SPEC_STATUS);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
link = val & (BIT(YT8521_LINK_STATUS_BIT));
|
|
if (link) {
|
|
link_utp = 1;
|
|
yt8521_adjust_status(phydev, val, 1);
|
|
} else {
|
|
link_utp = 0;
|
|
}
|
|
}
|
|
|
|
if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) {
|
|
/* reading Fiber */
|
|
ret = ytphy_write_ext(phydev, 0xa000, 2);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
val = phy_read(phydev, REG_PHY_SPEC_STATUS);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
/* note: below debug information is used to check multiple PHy ports. */
|
|
|
|
/* for fiber, from 1000m to 100m, there is not link down from 0x11,
|
|
* and check reg 1 to identify such case this is important for Linux
|
|
* kernel for that, missing linkdown event will cause problem.
|
|
*/
|
|
yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR);
|
|
yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR);
|
|
link = val & (BIT(YT8521_LINK_STATUS_BIT));
|
|
if (link && yt8521_fiber_latch_val != yt8521_fiber_curr_val) {
|
|
link = 0;
|
|
netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
|
|
__func__, phydev->mdio.addr, yt8521_fiber_latch_val,
|
|
yt8521_fiber_curr_val);
|
|
}
|
|
|
|
if (link) {
|
|
link_fiber = 1;
|
|
yt8521_adjust_status(phydev, val, 0);
|
|
} else {
|
|
link_fiber = 0;
|
|
}
|
|
}
|
|
|
|
if (link_utp || link_fiber) {
|
|
if (phydev->link == 0)
|
|
netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media: %s, mii reg 0x11 = 0x%x\n",
|
|
__func__, phydev->mdio.addr,
|
|
(link_utp && link_fiber) ? "UNKNOWN MEDIA" : (link_utp ? "UTP" : "Fiber"),
|
|
(unsigned int)val);
|
|
phydev->link = 1;
|
|
} else {
|
|
if (phydev->link == 1)
|
|
netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n",
|
|
__func__, phydev->mdio.addr);
|
|
phydev->link = 0;
|
|
}
|
|
|
|
/* utp or combo */
|
|
if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
|
|
if (link_fiber)
|
|
ytphy_write_ext(phydev, 0xa000, 2);
|
|
if (link_utp)
|
|
ytphy_write_ext(phydev, 0xa000, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int yt8521_suspend(struct phy_device *phydev)
|
|
{
|
|
#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
|
|
int value;
|
|
|
|
ytphy_write_ext(phydev, 0xa000, 0);
|
|
value = phy_read(phydev, MII_BMCR);
|
|
phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
|
|
|
|
ytphy_write_ext(phydev, 0xa000, 2);
|
|
value = phy_read(phydev, MII_BMCR);
|
|
phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
|
|
|
|
ytphy_write_ext(phydev, 0xa000, 0);
|
|
#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int yt8521_resume(struct phy_device *phydev)
|
|
{
|
|
int value, ret;
|
|
|
|
/* disable auto sleep */
|
|
value = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
|
|
if (value < 0)
|
|
return value;
|
|
|
|
value &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
|
|
|
|
ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, value);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
|
|
if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
|
|
ytphy_write_ext(phydev, 0xa000, 0);
|
|
value = phy_read(phydev, MII_BMCR);
|
|
phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
|
|
}
|
|
|
|
if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) {
|
|
ytphy_write_ext(phydev, 0xa000, 2);
|
|
value = phy_read(phydev, MII_BMCR);
|
|
phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
|
|
|
|
ytphy_write_ext(phydev, 0xa000, 0);
|
|
}
|
|
#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int yt8531_rxclk_duty_init(struct phy_device *phydev)
|
|
{
|
|
unsigned int value = 0x9696;
|
|
int ret = 0;
|
|
|
|
ret = ytphy_write_ext(phydev, 0xa040, 0xffff);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = ytphy_write_ext(phydev, 0xa041, 0xff);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = ytphy_write_ext(phydev, 0xa039, 0xbf00);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* nodelay duty = 0x9696 (default)
|
|
* fixed delay duty = 0x4040
|
|
* step delay 0xf duty = 0x4041
|
|
*/
|
|
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
|
phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
|
|
value = 0x4040;
|
|
|
|
ret = ytphy_write_ext(phydev, 0xa03a, value);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = ytphy_write_ext(phydev, 0xa03b, value);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = ytphy_write_ext(phydev, 0xa03c, value);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = ytphy_write_ext(phydev, 0xa03d, value);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = ytphy_write_ext(phydev, 0xa03e, value);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = ytphy_write_ext(phydev, 0xa03f, value);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int yt8531S_config_init(struct phy_device *phydev)
|
|
{
|
|
#if (YTPHY8531A_XTAL_INIT)
|
|
int ret = 0;
|
|
|
|
ret = yt8531a_xtal_init(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
#endif
|
|
|
|
return yt8521_config_init(phydev);
|
|
}
|
|
|
|
static int yt8531_config_init(struct phy_device *phydev)
|
|
{
|
|
int ret = 0, val;
|
|
|
|
#if (YTPHY8531A_XTAL_INIT)
|
|
ret = yt8531a_xtal_init(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
#endif
|
|
|
|
/* PHY_CLK_OUT 125M enabled (default) */
|
|
ret = ytphy_write_ext(phydev, 0xa012, 0xd0);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = yt8531_rxclk_duty_init(phydev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* RXC, PHY_CLK_OUT and RXData Drive strength:
|
|
* Drive strength of RXC = 6, PHY_CLK_OUT = 3, RXD0 = 4 (default 1.8v)
|
|
* If the io voltage is 3.3v, PHY_CLK_OUT = 2, set 0xa010 = 0xdacf
|
|
*/
|
|
ret = ytphy_write_ext(phydev, 0xa010, 0xdbcf);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Change 100M default BGS voltage from 0x294c to 0x274c */
|
|
val = ytphy_read_ext(phydev, 0x57);
|
|
val = (val & ~(0xf << 8)) | (7 << 8);
|
|
ret = ytphy_write_ext(phydev, 0x57, val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct phy_driver motorcomm_phy_drvs[] = {
|
|
{
|
|
PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
|
|
.name = "YT8511 Gigabit Ethernet",
|
|
.config_init = yt8511_config_init,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.read_page = yt8511_read_page,
|
|
.write_page = yt8511_write_page,
|
|
}, {
|
|
PHY_ID_MATCH_EXACT(PHY_ID_YT8512),
|
|
.name = "YT8512 Ethernet",
|
|
.config_init = yt8512_config_init,
|
|
.read_status = yt8512_read_status,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
PHY_ID_MATCH_EXACT(PHY_ID_YT8512B),
|
|
.name = "YT8512B Ethernet",
|
|
.config_init = yt8512_config_init,
|
|
.read_status = yt8512_read_status,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
}, {
|
|
/* same as 8521 */
|
|
PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
|
|
.name = "YT8531S Gigabit Ethernet",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.soft_reset = yt8521_soft_reset,
|
|
.aneg_done = yt8521_aneg_done,
|
|
.config_init = yt8531S_config_init,
|
|
.read_status = yt8521_read_status,
|
|
.suspend = yt8521_suspend,
|
|
.resume = yt8521_resume,
|
|
#if (YTPHY_WOL_FEATURE_ENABLE)
|
|
.get_wol = &ytphy_wol_feature_get,
|
|
.set_wol = &ytphy_wol_feature_set,
|
|
#endif
|
|
}, {
|
|
/* same as 8511 */
|
|
PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
|
|
.name = "YT8531 Gigabit Ethernet",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config_init = yt8531_config_init,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
#if (YTPHY_WOL_FEATURE_ENABLE)
|
|
.get_wol = &ytphy_wol_feature_get,
|
|
.set_wol = &ytphy_wol_feature_set,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
module_phy_driver(motorcomm_phy_drvs);
|
|
|
|
MODULE_DESCRIPTION("Motorcomm PHY driver");
|
|
MODULE_AUTHOR("Peter Geis");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
|
|
{ PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
|
|
{ PHY_ID_MATCH_EXACT(PHY_ID_YT8512) },
|
|
{ PHY_ID_MATCH_EXACT(PHY_ID_YT8512B) },
|
|
{ PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
|
|
{ PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
|
|
{ /* sentinal */ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
|