72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/*
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/grf_rk3128.h>
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#define GRF_GPIO1C_IOMUX 0x200080c0
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#define SDMMC_INTMASK 0x10214024
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#define READLATENCY_VAL 0x3f
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#define BUS_MSCH_QOS_BASE 0x10128014
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#define CPU_AXI_QOS_PRIORITY_BASE 0x1012f188
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#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
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((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
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#define CPU_AXI_CIF_QOS_PRIORITY_BASE 0x1012f208
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int arch_cpu_init(void)
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{
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/* We do some SoC one time setting here. */
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/* Read latency configure */
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writel(READLATENCY_VAL, BUS_MSCH_QOS_BASE);
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/* Set lcdc cpu axi qos priority level */
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writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_QOS_PRIORITY_BASE);
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/* Set GPIO1_C1 iomux to gpio, default sdcard_detn */
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writel(0x00040000, GRF_GPIO1C_IOMUX);
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#ifdef CONFIG_ROCKCHIP_RK3126
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/*
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* Disable interrupt, otherwise it always generates wakeup signal. This
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* is an IC hardware issue.
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*/
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writel(0, SDMMC_INTMASK);
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/* raise cif ddr qos priority */
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writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_CIF_QOS_PRIORITY_BASE);
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#endif
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return 0;
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}
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void board_debug_uart_init(void)
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{
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struct rk3128_grf * const grf __maybe_unused =
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(struct rk3128_grf * const)0x20008000;
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enum {
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/* UART2 */
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GPIO1C2_SHIFT = 4,
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GPIO1C2_MASK = GENMASK(5, 4),
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GPIO1C2_GPIO = 0,
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GPIO1C2_MMC0_D0 = 1,
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GPIO1C2_UART2_TX = 2,
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GPIO1C3_SHIFT = 6,
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GPIO1C3_MASK = GENMASK(7, 6),
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GPIO1C3_GPIO = 0,
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GPIO1C2_MMC0_D1 = 1,
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GPIO1C2_UART2_RX = 2,
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};
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rk_clrsetreg(&grf->gpio1c_iomux,
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GPIO1C2_MASK, GPIO1C2_UART2_TX << GPIO1C2_SHIFT);
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rk_clrsetreg(&grf->gpio1c_iomux,
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GPIO1C3_MASK, GPIO1C2_UART2_RX << GPIO1C3_SHIFT);
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}
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