574 lines
16 KiB
C
574 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip USB2.0 PHY with Naneng IP block driver
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*
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* Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <generic-phy.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <reset-uclass.h>
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#include <power/regulator.h>
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#define U2PHY_BIT_WRITEABLE_SHIFT 16
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struct rockchip_usb2phy;
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enum power_supply_type {
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POWER_SUPPLY_TYPE_UNKNOWN = 0,
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POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */
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POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */
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POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */
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POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */
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};
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enum rockchip_usb2phy_port_id {
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USB2PHY_PORT_OTG,
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USB2PHY_PORT_HOST,
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USB2PHY_NUM_PORTS,
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};
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struct usb2phy_reg {
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u32 offset;
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u32 bitend;
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u32 bitstart;
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u32 disable;
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u32 enable;
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};
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/**
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* struct rockchip_chg_det_reg: usb charger detect registers
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* @chg_valid: charge valid signal.
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* @phy_connect: PHY start handshake signal.
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* @chg_en: charge detector enable signal.
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* @chg_rst: charge detector reset signal, active high.
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*/
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struct rockchip_chg_det_reg {
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struct usb2phy_reg chg_valid;
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struct usb2phy_reg phy_connect;
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struct usb2phy_reg chg_en;
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struct usb2phy_reg chg_rst;
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};
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/**
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* struct rockchip_usb2phy_port_cfg: usb phy port configuration.
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* @bypass_otgsuspendm: otg-suspendm bypass control register.
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* 0: iddig; 1: grf.
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* @bvalidfall_det_en: vbus valid fall detection enable register.
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* @bvalidfall_det_st: vbus valid fall detection status register.
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* @bvalidfall_det_clr: vbus valid fall detection clear register.
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* @bvalidrise_det_en: vbus valid rise detection enable register.
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* @bvalidrise_det_st: vbus valid rise detection status register.
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* @bvalidrise_det_clr: vbus valid rise detection clear register.
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* @disconfall_det_en: host connect detection enable register.
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* @disconfall_det_st: host connect detection status register.
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* @disconfall_det_clr: host connect detection clear register.
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* @disconrise_det_en: host disconnect detection enable register.
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* @disconrise_det_st: host disconnect detection status register.
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* @disconrise_det_clr: host disconnect detection clear register.
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* @idfall_det_en: id fall detection enable register.
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* @idfall_det_st: id fall detection state register.
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* @idfall_det_clr: id fall detection clear register.
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* @idpullup: id pin pullup or pulldown control register.
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* @idrise_det_en: id rise detection enable register.
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* @idrise_det_st: id rise detection state register.
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* @idrise_det_clr: id rise detection clear register.
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* @ls_det_en: linestate detection enable register.
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* @ls_det_st: linestate detection state register.
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* @ls_det_clr: linestate detection clear register.
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* @phy_sus: phy suspend register.
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* @utmi_bvalid: utmi vbus bvalid status register.
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* @utmi_iddig: otg port id pin status register.
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* @utmi_hostdet: utmi host disconnect status register.
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*/
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struct rockchip_usb2phy_port_cfg {
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struct usb2phy_reg bypass_otgsuspendm;
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struct usb2phy_reg bvalidfall_det_en;
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struct usb2phy_reg bvalidfall_det_st;
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struct usb2phy_reg bvalidfall_det_clr;
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struct usb2phy_reg bvalidrise_det_en;
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struct usb2phy_reg bvalidrise_det_st;
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struct usb2phy_reg bvalidrise_det_clr;
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struct usb2phy_reg disconfall_det_en;
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struct usb2phy_reg disconfall_det_st;
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struct usb2phy_reg disconfall_det_clr;
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struct usb2phy_reg disconrise_det_en;
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struct usb2phy_reg disconrise_det_st;
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struct usb2phy_reg disconrise_det_clr;
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struct usb2phy_reg idfall_det_en;
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struct usb2phy_reg idfall_det_st;
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struct usb2phy_reg idfall_det_clr;
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struct usb2phy_reg idpullup;
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struct usb2phy_reg idrise_det_en;
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struct usb2phy_reg idrise_det_st;
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struct usb2phy_reg idrise_det_clr;
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struct usb2phy_reg ls_det_en;
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struct usb2phy_reg ls_det_st;
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struct usb2phy_reg ls_det_clr;
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struct usb2phy_reg phy_sus;
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struct usb2phy_reg utmi_bvalid;
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struct usb2phy_reg utmi_iddig;
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struct usb2phy_reg utmi_hostdet;
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};
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/**
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* struct rockchip_usb2phy_cfg: usb phy configuration.
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* @reg: the address offset of grf for usb-phy config.
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* @num_ports: specify how many ports that the phy has.
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* @phy_tuning: phy default parameters tuning.
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* @clkout_ctl: keep on/turn off output clk of phy.
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* @port_cfgs: ports register configuration, assigned by driver data.
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* @chg_det: charger detection registers.
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* @last: indicate the last one.
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*/
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struct rockchip_usb2phy_cfg {
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unsigned int reg;
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unsigned int num_ports;
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int (*phy_tuning)(struct rockchip_usb2phy *rphy);
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struct usb2phy_reg clkout_ctl;
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const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
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const struct rockchip_chg_det_reg chg_det;
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bool last;
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};
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/**
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* struct rockchip_usb2phy: usb2.0 phy driver data.
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* @grf: General Register Files register base.
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* @reset: power reset signal for phy.
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* @vbus_supply: vbus supply for usb host.
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* @phy_cfg: phy register configuration, assigned by driver data.
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*/
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struct rockchip_usb2phy {
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void __iomem *grf;
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struct reset_ctl *reset;
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struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
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const struct rockchip_usb2phy_cfg *phy_cfg;
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};
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static inline int property_enable(void __iomem *base,
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const struct usb2phy_reg *reg, bool en)
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{
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u32 val, mask, tmp;
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tmp = en ? reg->enable : reg->disable;
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT);
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writel(val, base + reg->offset);
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return 0;
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}
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static inline bool property_enabled(void __iomem *base,
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const struct usb2phy_reg *reg)
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{
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u32 tmp, orig;
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u32 mask = GENMASK(reg->bitend, reg->bitstart);
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orig = readl(base + reg->offset);
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tmp = (orig & mask) >> reg->bitstart;
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return tmp == reg->enable;
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}
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static const char *chg_to_string(enum power_supply_type chg_type)
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{
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switch (chg_type) {
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case POWER_SUPPLY_TYPE_USB:
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return "USB_SDP_CHARGER";
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case POWER_SUPPLY_TYPE_USB_DCP:
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return "USB_DCP_CHARGER";
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case POWER_SUPPLY_TYPE_USB_CDP:
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return "USB_CDP_CHARGER";
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case POWER_SUPPLY_TYPE_USB_FLOATING:
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return "USB_FLOATING_CHARGER";
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default:
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return "INVALID_CHARGER";
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}
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}
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int rockchip_chg_get_type(void)
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{
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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enum power_supply_type chg_type;
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struct rockchip_usb2phy *rphy;
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struct udevice *udev;
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bool chg_valid, phy_connect;
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int cnt;
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int ret;
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ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev);
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if (ret == -ENODEV) {
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ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev);
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if (ret) {
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pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret);
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return ret;
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}
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}
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rphy = dev_get_priv(udev);
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
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/* Check USB-Vbus status first */
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if (!property_enabled(rphy->grf, &port_cfg->utmi_bvalid)) {
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pr_info("%s: no charger found\n", __func__);
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return POWER_SUPPLY_TYPE_UNKNOWN;
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}
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reset_assert(rphy->reset);
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/* CHG_RST is set to 1'b0 to start charge detection */
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property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true);
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property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, false);
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for (cnt = 0; cnt < 12; cnt++) {
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mdelay(100);
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chg_valid = property_enabled(rphy->grf,
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&rphy->phy_cfg->chg_det.chg_valid);
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phy_connect =
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property_enabled(rphy->grf,
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&rphy->phy_cfg->chg_det.phy_connect);
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chg_type = (chg_valid << 1) | phy_connect;
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if (chg_type)
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goto compeleted;
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}
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compeleted:
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debug("charger = %s\n", chg_to_string(chg_type));
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mdelay(1);
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reset_deassert(rphy->reset);
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/* disable the chg detection module */
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property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true);
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property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false);
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return chg_type;
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}
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int rockchip_u2phy_vbus_detect(void)
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{
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int chg_type;
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chg_type = rockchip_chg_get_type();
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return (chg_type == POWER_SUPPLY_TYPE_USB ||
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chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0;
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}
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static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)
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{
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struct udevice *parent = phy->dev->parent;
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struct rockchip_usb2phy *rphy = dev_get_priv(parent);
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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void __iomem *base = rphy->grf;
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struct udevice *vbus = NULL;
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bool iddig = true;
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if (phy->id == USB2PHY_PORT_HOST) {
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vbus = rphy->vbus_supply[USB2PHY_PORT_HOST];
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} else if (phy->id == USB2PHY_PORT_OTG) {
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
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if (port_cfg->utmi_iddig.offset) {
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iddig = property_enabled(base, &port_cfg->utmi_iddig);
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if (!iddig)
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vbus = rphy->vbus_supply[USB2PHY_PORT_OTG];
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}
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}
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return vbus;
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}
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static int rockchip_usb2phy_init(struct phy *phy)
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{
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struct udevice *parent = phy->dev->parent;
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struct rockchip_usb2phy *rphy = dev_get_priv(parent);
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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if (phy->id == USB2PHY_PORT_OTG) {
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
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} else if (phy->id == USB2PHY_PORT_HOST) {
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
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} else {
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dev_err(phy->dev, "phy id %lu not support", phy->id);
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return -EINVAL;
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}
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property_enable(rphy->grf, &port_cfg->phy_sus, false);
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/* waiting for the utmi_clk to become stable */
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udelay(2000);
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return 0;
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}
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static int rockchip_usb2phy_exit(struct phy *phy)
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{
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struct udevice *parent = phy->dev->parent;
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struct rockchip_usb2phy *rphy = dev_get_priv(parent);
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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if (phy->id == USB2PHY_PORT_OTG) {
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
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} else if (phy->id == USB2PHY_PORT_HOST) {
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
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} else {
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dev_err(phy->dev, "phy id %lu not support", phy->id);
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return -EINVAL;
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}
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property_enable(rphy->grf, &port_cfg->phy_sus, true);
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return 0;
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}
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static int rockchip_usb2phy_power_on(struct phy *phy)
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{
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struct udevice *vbus = NULL;
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int ret;
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vbus = rockchip_usb2phy_check_vbus(phy);
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if (vbus) {
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ret = regulator_set_enable(vbus, true);
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if (ret) {
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pr_err("%s: Failed to en VBus supply\n", __func__);
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return ret;
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}
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}
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return 0;
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}
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static int rockchip_usb2phy_power_off(struct phy *phy)
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{
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struct udevice *vbus = NULL;
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int ret;
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vbus = rockchip_usb2phy_check_vbus(phy);
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if (vbus) {
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ret = regulator_set_enable(vbus, false);
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if (ret) {
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pr_err("%s: Failed to dis VBus supply\n", __func__);
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return ret;
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}
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}
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return 0;
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}
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static int rockchip_usb2phy_of_xlate(struct phy *phy,
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struct ofnode_phandle_args *args)
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{
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const char *dev_name = phy->dev->name;
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struct udevice *parent = phy->dev->parent;
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struct rockchip_usb2phy *rphy = dev_get_priv(parent);
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if (!strcasecmp(dev_name, "host-port")) {
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phy->id = USB2PHY_PORT_HOST;
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device_get_supply_regulator(phy->dev, "phy-supply",
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&rphy->vbus_supply[USB2PHY_PORT_HOST]);
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} else if (!strcasecmp(dev_name, "otg-port")) {
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phy->id = USB2PHY_PORT_OTG;
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device_get_supply_regulator(phy->dev, "phy-supply",
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&rphy->vbus_supply[USB2PHY_PORT_OTG]);
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} else {
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pr_err("%s: invalid dev name\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static int rockchip_usb2phy_bind(struct udevice *dev)
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{
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struct udevice *child;
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ofnode subnode;
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const char *node_name;
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int ret;
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dev_for_each_subnode(subnode, dev) {
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if (!ofnode_valid(subnode)) {
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debug("%s: %s subnode not found", __func__, dev->name);
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return -ENXIO;
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}
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node_name = ofnode_get_name(subnode);
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debug("%s: subnode %s\n", __func__, node_name);
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ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
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node_name, subnode, &child);
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if (ret) {
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pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n",
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__func__, node_name);
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return ret;
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}
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}
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return 0;
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}
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static int rockchip_usb2phy_probe(struct udevice *dev)
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{
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const struct rockchip_usb2phy_cfg *phy_cfgs;
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struct rockchip_usb2phy *rphy = dev_get_priv(dev);
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u32 reg, index;
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rphy->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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/* get phy power reset control */
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if (reset_get_by_name(dev, "u2phy", rphy->reset)) {
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pr_err("can't get phy power reset for %s", dev->name);
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return -EINVAL;
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}
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if (rphy->grf <= 0) {
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dev_err(dev, "get syscon grf failed\n");
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return -EINVAL;
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}
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if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) {
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dev_err(dev, "could not read reg\n");
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return -EINVAL;
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}
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phy_cfgs =
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(const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev);
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if (!phy_cfgs) {
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dev_err(dev, "unable to get phy_cfgs\n");
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return -EINVAL;
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}
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/* find out a proper config which can be matched with dt. */
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index = 0;
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do {
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if (phy_cfgs[index].reg == reg) {
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rphy->phy_cfg = &phy_cfgs[index];
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break;
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}
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} while (!phy_cfgs[index++].last);
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if (!rphy->phy_cfg) {
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dev_err(dev, "no phy-config can be matched\n");
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return -EINVAL;
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}
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if (rphy->phy_cfg->phy_tuning)
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rphy->phy_cfg->phy_tuning(rphy);
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return 0;
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}
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static int rv1126_usb2phy_tuning(struct rockchip_usb2phy *rphy)
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{
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return 0;
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}
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static struct phy_ops rockchip_usb2phy_ops = {
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.init = rockchip_usb2phy_init,
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.exit = rockchip_usb2phy_exit,
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.power_on = rockchip_usb2phy_power_on,
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.power_off = rockchip_usb2phy_power_off,
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.of_xlate = rockchip_usb2phy_of_xlate,
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|
};
|
|
|
|
static const struct rockchip_usb2phy_cfg rv1126_phy_cfgs[] = {
|
|
{
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|
.reg = 0xff4c0000,
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|
.num_ports = 1,
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|
.phy_tuning = rv1126_usb2phy_tuning,
|
|
.clkout_ctl = { 0x10230, 14, 14, 0, 1 },
|
|
.port_cfgs = {
|
|
[USB2PHY_PORT_OTG] = {
|
|
.bypass_otgsuspendm = { 0x10234, 12, 12, 0, 1 },
|
|
.bvalidfall_det_en = { 0x10300, 3, 3, 0, 1 },
|
|
.bvalidfall_det_st = { 0x10304, 3, 3, 0, 1 },
|
|
.bvalidfall_det_clr = { 0x10308, 3, 3, 0, 1 },
|
|
.bvalidrise_det_en = { 0x10300, 2, 2, 0, 1 },
|
|
.bvalidrise_det_st = { 0x10304, 2, 2, 0, 1 },
|
|
.bvalidrise_det_clr = { 0x10308, 2, 2, 0, 1 },
|
|
.disconfall_det_en = { 0x10300, 7, 7, 0, 1 },
|
|
.disconfall_det_st = { 0x10304, 7, 7, 0, 1 },
|
|
.disconfall_det_clr = { 0x10308, 7, 7, 0, 1 },
|
|
.disconrise_det_en = { 0x10300, 6, 6, 0, 1 },
|
|
.disconrise_det_st = { 0x10304, 6, 6, 0, 1 },
|
|
.disconrise_det_clr = { 0x10308, 6, 6, 0, 1 },
|
|
.idfall_det_en = { 0x10300, 5, 5, 0, 1 },
|
|
.idfall_det_st = { 0x10304, 5, 5, 0, 1 },
|
|
.idfall_det_clr = { 0x10308, 5, 5, 0, 1 },
|
|
.idpullup = { 0x10230, 11, 11, 0, 1 },
|
|
.idrise_det_en = { 0x10300, 4, 4, 0, 1 },
|
|
.idrise_det_st = { 0x10304, 4, 4, 0, 1 },
|
|
.idrise_det_clr = { 0x10308, 4, 4, 0, 1 },
|
|
.ls_det_en = { 0x10300, 0, 0, 0, 1 },
|
|
.ls_det_st = { 0x10304, 0, 0, 0, 1 },
|
|
.ls_det_clr = { 0x10308, 0, 0, 0, 1 },
|
|
.phy_sus = { 0x10230, 8, 0, 0x052, 0x1d9 },
|
|
.utmi_bvalid = { 0x10248, 9, 9, 0, 1 },
|
|
.utmi_iddig = { 0x10248, 6, 6, 0, 1 },
|
|
.utmi_hostdet = { 0x10248, 7, 7, 0, 1 },
|
|
}
|
|
},
|
|
.chg_det = {
|
|
.chg_en = { 0x10234, 14, 14, 0, 1 },
|
|
.chg_rst = { 0x10234, 15, 15, 0, 1 },
|
|
.chg_valid = { 0x10248, 12, 12, 0, 1 },
|
|
.phy_connect = { 0x10248, 13, 13, 0, 1 },
|
|
},
|
|
},
|
|
{
|
|
.reg = 0xff4c8000,
|
|
.num_ports = 1,
|
|
.phy_tuning = rv1126_usb2phy_tuning,
|
|
.clkout_ctl = { 0x10238, 9, 9, 0, 1 },
|
|
.port_cfgs = {
|
|
[USB2PHY_PORT_HOST] = {
|
|
.disconfall_det_en = { 0x10300, 9, 9, 0, 1 },
|
|
.disconfall_det_st = { 0x10304, 9, 9, 0, 1 },
|
|
.disconfall_det_clr = { 0x10308, 9, 9, 0, 1 },
|
|
.disconrise_det_en = { 0x10300, 8, 8, 0, 1 },
|
|
.disconrise_det_st = { 0x10304, 8, 8, 0, 1 },
|
|
.disconrise_det_clr = { 0x10308, 8, 8, 0, 1 },
|
|
.ls_det_en = { 0x10300, 1, 1, 0, 1 },
|
|
.ls_det_st = { 0x10304, 1, 1, 0, 1 },
|
|
.ls_det_clr = { 0x10308, 1, 1, 0, 1 },
|
|
.phy_sus = { 0x10238, 3, 0, 0x2, 0x9 },
|
|
.utmi_hostdet = { 0x10248, 23, 23, 0, 1 },
|
|
}
|
|
},
|
|
.chg_det = {
|
|
.chg_en = { 0x10238, 7, 7, 0, 1 },
|
|
.chg_rst = { 0x10238, 8, 8, 0, 1 },
|
|
.chg_valid = { 0x10248, 28, 28, 0, 1 },
|
|
.phy_connect = { 0x10248, 29, 29, 0, 1 },
|
|
},
|
|
.last = true,
|
|
},
|
|
};
|
|
|
|
static const struct udevice_id rockchip_usb2phy_ids[] = {
|
|
{ .compatible = "rockchip,rv1126-usb2phy", .data = (ulong)&rv1126_phy_cfgs },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_usb2phy_port) = {
|
|
.name = "rockchip_usb2phy_port",
|
|
.id = UCLASS_PHY,
|
|
.ops = &rockchip_usb2phy_ops,
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_usb2phy) = {
|
|
.name = "rockchip_usb2phy",
|
|
.id = UCLASS_PHY,
|
|
.of_match = rockchip_usb2phy_ids,
|
|
.probe = rockchip_usb2phy_probe,
|
|
.bind = rockchip_usb2phy_bind,
|
|
.priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
|
|
};
|