75 lines
2.3 KiB
Smali
75 lines
2.3 KiB
Smali
# Copyright (C) 2016 The Android Open Source Project
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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.class public LIrreducibleLoop;
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.super Ljava/lang/Object;
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# Test case where liveness analysis produces linear order where loop blocks are
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# not adjacent. This revealed a bug in our SSA builder, where a dead loop phi would
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# be replaced by its incoming input during SsaRedundantPhiElimination.
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# Check that the outer loop suspend check environment only has the parameter vreg.
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## CHECK-START: int IrreducibleLoop.liveness(int) builder (after)
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## CHECK-DAG: <<Phi:i\d+>> Phi reg:4 loop:{{B\d+}} irreducible:false
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## CHECK-DAG: SuspendCheck env:[[_,_,_,_,<<Phi>>]] loop:{{B\d+}} irreducible:false
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# Check that the linear order has non-adjacent loop blocks.
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## CHECK-START: int IrreducibleLoop.liveness(int) liveness (after)
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## CHECK-DAG: Mul liveness:<<LPreEntry2:\d+>>
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## CHECK-DAG: Add liveness:<<LBackEdge1:\d+>>
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## CHECK-EVAL: <<LBackEdge1>> < <<LPreEntry2>>
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.method public static liveness(I)I
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.registers 5
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const-string v1, "MyString"
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:header1
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if-eqz p0, :body1
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:exit
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return p0
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:body1
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# The test will generate an incorrect linear order when the following IF swaps
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# its successors. To do that, load a boolean value and compare NotEqual to 1.
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sget-boolean v2, LIrreducibleLoop;->f:Z
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const v3, 1
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if-ne v2, v3, :pre_header2
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:pre_entry2
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# Add a marker on the irreducible loop entry.
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mul-int/2addr p0, p0
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goto :back_edge2
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:back_edge2
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goto :header2
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:header2
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if-eqz p0, :back_edge2
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:back_edge1
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# Add a marker on the outer loop back edge.
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add-int/2addr p0, p0
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# Set a wide register, to have v1 undefined at the back edge.
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const-wide/16 v0, 0x1
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goto :header1
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:pre_header2
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goto :header2
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.end method
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.field public static f:Z
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