330 lines
8.9 KiB
YAML
330 lines
8.9 KiB
YAML
# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
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# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -regbankselect-greedy -o - 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
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# REQUIRES: global-isel
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--- |
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; ModuleID = 'generic-virtual-registers-type-error.mir'
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-apple-ios"
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define void @defaultMapping() {
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entry:
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ret void
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}
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define void @defaultMappingVector() {
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entry:
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ret void
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}
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define void @defaultMapping1Repair() {
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entry:
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ret void
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}
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define void @defaultMapping2Repairs() {
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entry:
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ret void
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}
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define void @defaultMappingDefRepair() {
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entry:
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ret void
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}
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define void @phiPropagation(i32* %src, i32* %dst, i1 %cond) {
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entry:
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%srcVal = load i32, i32* %src
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br i1 %cond, label %end, label %then
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then:
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%res = add i32 %srcVal, 36
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br label %end
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end:
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%toStore = phi i32 [ %srcVal, %entry ], [ %res, %then ]
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store i32 %toStore, i32* %dst
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ret void
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}
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define void @defaultMappingUseRepairPhysReg() {
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entry:
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ret void
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}
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define void @defaultMappingDefRepairPhysReg() {
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entry:
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ret void
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}
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define void @greedyMappingOr() {
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entry:
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ret void
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}
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define void @greedyMappingOrWithConstraints() {
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entry:
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ret void
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}
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...
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---
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# Check that we assign a relevant register bank for %0.
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# Based on the type i32, this should be gpr.
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name: defaultMapping
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0
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; CHECK: %0(32) = G_ADD i32 %x0
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%0(32) = G_ADD i32 %x0, %x0
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...
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---
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# Check that we assign a relevant register bank for %0.
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# Based on the type <2 x i32>, this should be fpr.
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# FPR is used for both floating point and vector registers.
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name: defaultMappingVector
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0.entry:
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liveins: %d0
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; CHECK: %0(32) = G_ADD <2 x i32> %d0
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%0(32) = G_ADD <2 x i32> %d0, %d0
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...
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---
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# Check that we repair the assignment for %0.
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# Indeed based on the source of the copy it should live
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# in FPR, but at the use, it should be GPR.
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name: defaultMapping1Repair
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr }
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# CHECK-NEXT: - { id: 1, class: gpr }
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# CHECK-NEXT: - { id: 2, class: gpr }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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liveins: %s0, %x0
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; CHECK: %0(32) = COPY %s0
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; CHECK-NEXT: %2(32) = COPY %0
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; CHECK-NEXT: %1(32) = G_ADD i32 %2, %x0
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%0(32) = COPY %s0
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%1(32) = G_ADD i32 %0, %x0
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...
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# Check that we repair the assignment for %0 differently for both uses.
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name: defaultMapping2Repairs
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr }
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# CHECK-NEXT: - { id: 1, class: gpr }
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# CHECK-NEXT: - { id: 2, class: gpr }
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# CHECK-NEXT: - { id: 3, class: gpr }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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liveins: %s0, %x0
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; CHECK: %0(32) = COPY %s0
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; CHECK-NEXT: %2(32) = COPY %0
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; CHECK-NEXT: %3(32) = COPY %0
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; CHECK-NEXT: %1(32) = G_ADD i32 %2, %3
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%0(32) = COPY %s0
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%1(32) = G_ADD i32 %0, %0
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...
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---
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# Check that we repair the definition of %1.
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# %1 is forced to be into FPR, but its definition actually
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# requires that it lives in GPR. Make sure regbankselect
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# fixes that.
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name: defaultMappingDefRepair
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr }
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# CHECK-NEXT: - { id: 1, class: fpr }
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# CHECK-NEXT: - { id: 2, class: gpr }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: fpr }
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body: |
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bb.0.entry:
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liveins: %w0
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; CHECK: %0(32) = COPY %w0
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; CHECK-NEXT: %2(32) = G_ADD i32 %0, %w0
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; CHECK-NEXT: %1(32) = COPY %2
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%0(32) = COPY %w0
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%1(32) = G_ADD i32 %0, %w0
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...
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---
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# Check that we are able to propagate register banks from phis.
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name: phiPropagation
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isSSA: true
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tracksRegLiveness: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr32 }
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# CHECK-NEXT: - { id: 1, class: gpr64sp }
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# CHECK-NEXT: - { id: 2, class: gpr32 }
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# CHECK-NEXT: - { id: 3, class: gpr }
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# CHECK-NEXT: - { id: 4, class: gpr }
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr64sp }
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- { id: 2, class: gpr32 }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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body: |
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bb.0.entry:
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successors: %bb.2.end, %bb.1.then
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liveins: %x0, %x1, %w2
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%0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src)
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%1 = COPY %x1
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%2 = COPY %w2
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TBNZW killed %2, 0, %bb.2.end
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bb.1.then:
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successors: %bb.2.end
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%3(32) = G_ADD i32 %0, %0
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bb.2.end:
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%4(32) = PHI %0, %bb.0.entry, %3, %bb.1.then
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STRWui killed %4, killed %1, 0 :: (store 4 into %ir.dst)
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RET_ReallyLR
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...
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---
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# Make sure we can repair physical register uses as well.
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name: defaultMappingUseRepairPhysReg
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr }
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# CHECK-NEXT: - { id: 1, class: gpr }
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# CHECK-NEXT: - { id: 2, class: gpr }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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liveins: %w0, %s0
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; CHECK: %0(32) = COPY %w0
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; CHECK-NEXT: %2(32) = COPY %s0
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; CHECK-NEXT: %1(32) = G_ADD i32 %0, %2
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%0(32) = COPY %w0
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%1(32) = G_ADD i32 %0, %s0
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...
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---
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# Make sure we can repair physical register defs.
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name: defaultMappingDefRepairPhysReg
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr }
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# CHECK-NEXT: - { id: 1, class: gpr }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0.entry:
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liveins: %w0
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; CHECK: %0(32) = COPY %w0
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; CHECK-NEXT: %1(32) = G_ADD i32 %0, %0
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; CHECK-NEXT: %s0 = COPY %1
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%0(32) = COPY %w0
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%s0 = G_ADD i32 %0, %0
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...
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---
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# Check that the greedy mode is able to switch the
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# G_OR instruction from fpr to gpr.
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name: greedyMappingOr
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr }
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# CHECK-NEXT: - { id: 1, class: gpr }
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# Fast mode maps vector instruction on FPR.
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# FAST-NEXT: - { id: 2, class: fpr }
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# Fast mode needs two extra copies.
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# FAST-NEXT: - { id: 3, class: fpr }
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# FAST-NEXT: - { id: 4, class: fpr }
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# Greedy mode coalesce the computation on the GPR register
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# because it is the cheapest.
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# GREEDY-NEXT: - { id: 2, class: gpr }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0, %x1
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; CHECK: %0(64) = COPY %x0
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; CHECK-NEXT: %1(64) = COPY %x1
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; Fast mode tries to reuse the source of the copy for the destination.
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; Now, the default mapping says that %0 and %1 need to be in FPR.
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; The repairing code insert two copies to materialize that.
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; FAST-NEXT: %3(64) = COPY %0
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; FAST-NEXT: %4(64) = COPY %1
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; The mapping of G_OR is on FPR.
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; FAST-NEXT: %2(64) = G_OR <2 x i32> %3, %4
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; Greedy mode remapped the instruction on the GPR bank.
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; GREEDY-NEXT: %2(64) = G_OR <2 x i32> %0, %1
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%0(64) = COPY %x0
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%1(64) = COPY %x1
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%2(64) = G_OR <2 x i32> %0, %1
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...
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---
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# Check that the greedy mode is able to switch the
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# G_OR instruction from fpr to gpr, while still honoring
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# %2 constraint.
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name: greedyMappingOrWithConstraints
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isSSA: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr }
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# CHECK-NEXT: - { id: 1, class: gpr }
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# CHECK-NEXT: - { id: 2, class: fpr }
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# Fast mode maps vector instruction on FPR.
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# Fast mode needs two extra copies.
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# FAST-NEXT: - { id: 3, class: fpr }
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# FAST-NEXT: - { id: 4, class: fpr }
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# Greedy mode coalesce the computation on the GPR register because it
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# is the cheapest, but will need one extra copy to materialize %2 into a FPR.
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# GREEDY-NEXT: - { id: 3, class: gpr }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: fpr }
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body: |
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bb.0.entry:
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liveins: %x0, %x1
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; CHECK: %0(64) = COPY %x0
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; CHECK-NEXT: %1(64) = COPY %x1
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; Fast mode tries to reuse the source of the copy for the destination.
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; Now, the default mapping says that %0 and %1 need to be in FPR.
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; The repairing code insert two copies to materialize that.
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; FAST-NEXT: %3(64) = COPY %0
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; FAST-NEXT: %4(64) = COPY %1
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; The mapping of G_OR is on FPR.
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; FAST-NEXT: %2(64) = G_OR <2 x i32> %3, %4
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; Greedy mode remapped the instruction on the GPR bank.
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; GREEDY-NEXT: %3(64) = G_OR <2 x i32> %0, %1
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; We need to keep %2 into FPR because we do not know anything about it.
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; GREEDY-NEXT: %2(64) = COPY %3
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%0(64) = COPY %x0
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%1(64) = COPY %x1
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%2(64) = G_OR <2 x i32> %0, %1
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...
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