336 lines
14 KiB
LLVM
336 lines
14 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-EVEN
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; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-ODD
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; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN
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; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD
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; The following tests use the balance-fp-ops feature, and should be independent of
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; the target cpu.
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; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN --check-prefix CHECK-BALFP
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; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD --check-prefix CHECK-BALFP
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; Test the AArch64A57FPLoadBalancing pass. This pass relies heavily on register allocation, so
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; our test strategy is to:
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; * Force the pass to always perform register swapping even if the dest register is of the
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; correct color already (-force-all)
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; * Force the pass to ignore all hints it obtained from regalloc (-deterministic-balance),
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; and run it twice, once where it always hints odd, and once where it always hints even.
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;
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; We then use regex magic to check that in the two cases the register allocation is
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; different; this is what gives us the testing coverage and distinguishes cases where
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; the pass has done some work versus accidental regalloc.
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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; Non-overlapping groups - shouldn't need any changing at all.
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; CHECK-LABEL: f1:
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; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
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; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
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; CHECK: fmadd [[x]]
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; CHECK: fmsub [[x]]
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; CHECK: fmadd [[x]]
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; CHECK: str [[x]]
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define void @f1(double* nocapture readonly %p, double* nocapture %q) #0 {
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entry:
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%0 = load double, double* %p, align 8
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%arrayidx1 = getelementptr inbounds double, double* %p, i64 1
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%1 = load double, double* %arrayidx1, align 8
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%arrayidx2 = getelementptr inbounds double, double* %p, i64 2
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%2 = load double, double* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds double, double* %p, i64 3
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%3 = load double, double* %arrayidx3, align 8
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%arrayidx4 = getelementptr inbounds double, double* %p, i64 4
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%4 = load double, double* %arrayidx4, align 8
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%mul = fmul fast double %0, %1
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%add = fadd fast double %mul, %4
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%mul5 = fmul fast double %1, %2
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%add6 = fadd fast double %mul5, %add
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%mul7 = fmul fast double %1, %3
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%sub = fsub fast double %add6, %mul7
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%mul8 = fmul fast double %2, %3
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%add9 = fadd fast double %mul8, %sub
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store double %add9, double* %q, align 8
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%arrayidx11 = getelementptr inbounds double, double* %p, i64 5
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%5 = load double, double* %arrayidx11, align 8
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%arrayidx12 = getelementptr inbounds double, double* %p, i64 6
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%6 = load double, double* %arrayidx12, align 8
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%arrayidx13 = getelementptr inbounds double, double* %p, i64 7
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%7 = load double, double* %arrayidx13, align 8
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%mul15 = fmul fast double %6, %7
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%mul16 = fmul fast double %0, %5
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%add17 = fadd fast double %mul16, %mul15
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%mul18 = fmul fast double %5, %6
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%add19 = fadd fast double %mul18, %add17
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%arrayidx20 = getelementptr inbounds double, double* %q, i64 1
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store double %add19, double* %arrayidx20, align 8
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ret void
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}
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; Overlapping groups - coloring needed.
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; CHECK-LABEL: f2:
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; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
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; CHECK-EVEN: fmul [[y:d[0-9]*[13579]]]
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; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
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; CHECK-ODD: fmul [[y:d[0-9]*[02468]]]
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; CHECK: fmadd [[x]]
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; CHECK: fmadd [[y]]
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; CHECK: fmsub [[x]]
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; CHECK: fmadd [[y]]
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; CHECK: fmadd [[x]]
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; CHECK-BALFP: stp [[x]], [[y]]
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; CHECK-A53-DAG: str [[x]]
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; CHECK-A53-DAG: str [[y]]
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define void @f2(double* nocapture readonly %p, double* nocapture %q) #0 {
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entry:
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%0 = load double, double* %p, align 8
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%arrayidx1 = getelementptr inbounds double, double* %p, i64 1
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%1 = load double, double* %arrayidx1, align 8
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%arrayidx2 = getelementptr inbounds double, double* %p, i64 2
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%2 = load double, double* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds double, double* %p, i64 3
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%3 = load double, double* %arrayidx3, align 8
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%arrayidx4 = getelementptr inbounds double, double* %p, i64 4
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%4 = load double, double* %arrayidx4, align 8
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%arrayidx5 = getelementptr inbounds double, double* %p, i64 5
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%5 = load double, double* %arrayidx5, align 8
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%arrayidx6 = getelementptr inbounds double, double* %p, i64 6
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%6 = load double, double* %arrayidx6, align 8
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%arrayidx7 = getelementptr inbounds double, double* %p, i64 7
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%7 = load double, double* %arrayidx7, align 8
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%mul = fmul fast double %0, %1
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%add = fadd fast double %mul, %7
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%mul8 = fmul fast double %5, %6
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%mul9 = fmul fast double %1, %2
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%add10 = fadd fast double %mul9, %add
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%mul11 = fmul fast double %3, %4
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%add12 = fadd fast double %mul11, %mul8
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%mul13 = fmul fast double %1, %3
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%sub = fsub fast double %add10, %mul13
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%mul14 = fmul fast double %4, %5
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%add15 = fadd fast double %mul14, %add12
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%mul16 = fmul fast double %2, %3
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%add17 = fadd fast double %mul16, %sub
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store double %add17, double* %q, align 8
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%arrayidx19 = getelementptr inbounds double, double* %q, i64 1
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store double %add15, double* %arrayidx19, align 8
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ret void
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}
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; Dest register is live on block exit - fixup needed.
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; CHECK-LABEL: f3:
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; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
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; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
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; CHECK: fmadd [[x]]
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; CHECK: fmsub [[x]]
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; CHECK: fmadd [[y:d[0-9]+]], {{.*}}, [[x]]
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; CHECK: str [[y]]
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define void @f3(double* nocapture readonly %p, double* nocapture %q) #0 {
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entry:
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%0 = load double, double* %p, align 8
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%arrayidx1 = getelementptr inbounds double, double* %p, i64 1
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%1 = load double, double* %arrayidx1, align 8
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%arrayidx2 = getelementptr inbounds double, double* %p, i64 2
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%2 = load double, double* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds double, double* %p, i64 3
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%3 = load double, double* %arrayidx3, align 8
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%arrayidx4 = getelementptr inbounds double, double* %p, i64 4
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%4 = load double, double* %arrayidx4, align 8
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%mul = fmul fast double %0, %1
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%add = fadd fast double %mul, %4
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%mul5 = fmul fast double %1, %2
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%add6 = fadd fast double %mul5, %add
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%mul7 = fmul fast double %1, %3
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%sub = fsub fast double %add6, %mul7
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%mul8 = fmul fast double %2, %3
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%add9 = fadd fast double %mul8, %sub
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%cmp = fcmp oeq double %3, 0.000000e+00
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void bitcast (void (...)* @g to void ()*)() #2
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br label %if.end
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if.end: ; preds = %if.then, %entry
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store double %add9, double* %q, align 8
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ret void
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}
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declare void @g(...) #1
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; Single precision version of f2.
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; CHECK-LABEL: f4:
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; CHECK-EVEN: fmadd [[x:s[0-9]*[02468]]]
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; CHECK-EVEN: fmul [[y:s[0-9]*[13579]]]
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; CHECK-ODD: fmadd [[x:s[0-9]*[13579]]]
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; CHECK-ODD: fmul [[y:s[0-9]*[02468]]]
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; CHECK: fmadd [[x]]
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; CHECK: fmadd [[y]]
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; CHECK: fmsub [[x]]
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; CHECK: fmadd [[y]]
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; CHECK: fmadd [[x]]
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; CHECK-BALFP: stp [[x]], [[y]]
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; CHECK-A53-DAG: str [[x]]
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; CHECK-A53-DAG: str [[y]]
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define void @f4(float* nocapture readonly %p, float* nocapture %q) #0 {
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entry:
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%0 = load float, float* %p, align 4
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%arrayidx1 = getelementptr inbounds float, float* %p, i64 1
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%1 = load float, float* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds float, float* %p, i64 2
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%2 = load float, float* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds float, float* %p, i64 3
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%3 = load float, float* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds float, float* %p, i64 4
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%4 = load float, float* %arrayidx4, align 4
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%arrayidx5 = getelementptr inbounds float, float* %p, i64 5
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%5 = load float, float* %arrayidx5, align 4
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%arrayidx6 = getelementptr inbounds float, float* %p, i64 6
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%6 = load float, float* %arrayidx6, align 4
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%arrayidx7 = getelementptr inbounds float, float* %p, i64 7
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%7 = load float, float* %arrayidx7, align 4
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%mul = fmul fast float %0, %1
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%add = fadd fast float %mul, %7
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%mul8 = fmul fast float %5, %6
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%mul9 = fmul fast float %1, %2
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%add10 = fadd fast float %mul9, %add
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%mul11 = fmul fast float %3, %4
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%add12 = fadd fast float %mul11, %mul8
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%mul13 = fmul fast float %1, %3
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%sub = fsub fast float %add10, %mul13
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%mul14 = fmul fast float %4, %5
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%add15 = fadd fast float %mul14, %add12
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%mul16 = fmul fast float %2, %3
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%add17 = fadd fast float %mul16, %sub
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store float %add17, float* %q, align 4
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%arrayidx19 = getelementptr inbounds float, float* %q, i64 1
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store float %add15, float* %arrayidx19, align 4
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ret void
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}
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; Single precision version of f3
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; CHECK-LABEL: f5:
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; CHECK-EVEN: fmadd [[x:s[0-9]*[02468]]]
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; CHECK-ODD: fmadd [[x:s[0-9]*[13579]]]
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; CHECK: fmadd [[x]]
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; CHECK: fmsub [[x]]
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; CHECK: fmadd [[y:s[0-9]+]], {{.*}}, [[x]]
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; CHECK: str [[y]]
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define void @f5(float* nocapture readonly %p, float* nocapture %q) #0 {
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entry:
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%0 = load float, float* %p, align 4
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%arrayidx1 = getelementptr inbounds float, float* %p, i64 1
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%1 = load float, float* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds float, float* %p, i64 2
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%2 = load float, float* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds float, float* %p, i64 3
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%3 = load float, float* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds float, float* %p, i64 4
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%4 = load float, float* %arrayidx4, align 4
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%mul = fmul fast float %0, %1
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%add = fadd fast float %mul, %4
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%mul5 = fmul fast float %1, %2
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%add6 = fadd fast float %mul5, %add
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%mul7 = fmul fast float %1, %3
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%sub = fsub fast float %add6, %mul7
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%mul8 = fmul fast float %2, %3
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%add9 = fadd fast float %mul8, %sub
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%cmp = fcmp oeq float %3, 0.000000e+00
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void bitcast (void (...)* @g to void ()*)() #2
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br label %if.end
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if.end: ; preds = %if.then, %entry
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store float %add9, float* %q, align 4
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ret void
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}
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; Test that regmask clobbering stops a chain sequence.
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; CHECK-LABEL: f6:
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; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
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; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
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; CHECK: fmadd [[x]]
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; CHECK: fmsub [[x]]
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; CHECK: fmadd d0, {{.*}}, [[x]]
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; CHECK: bl hh
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; CHECK: str d0
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define void @f6(double* nocapture readonly %p, double* nocapture %q) #0 {
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entry:
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%0 = load double, double* %p, align 8
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%arrayidx1 = getelementptr inbounds double, double* %p, i64 1
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%1 = load double, double* %arrayidx1, align 8
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%arrayidx2 = getelementptr inbounds double, double* %p, i64 2
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%2 = load double, double* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds double, double* %p, i64 3
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%3 = load double, double* %arrayidx3, align 8
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%arrayidx4 = getelementptr inbounds double, double* %p, i64 4
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%4 = load double, double* %arrayidx4, align 8
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%mul = fmul fast double %0, %1
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%add = fadd fast double %mul, %4
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%mul5 = fmul fast double %1, %2
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%add6 = fadd fast double %mul5, %add
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%mul7 = fmul fast double %1, %3
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%sub = fsub fast double %add6, %mul7
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%mul8 = fmul fast double %2, %3
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%add9 = fadd fast double %mul8, %sub
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%call = tail call double @hh(double %add9) #2
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store double %call, double* %q, align 8
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ret void
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}
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declare double @hh(double) #1
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; Check that we correctly deal with repeated operands.
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; The following testcase creates:
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; %D1<def> = FADDDrr %D0<kill>, %D0
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; We'll get a crash if we naively look at the first operand, remove it
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; from the substitution list then look at the second operand.
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; CHECK: fmadd [[x:d[0-9]+]]
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; CHECK: fadd d1, [[x]], [[x]]
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define void @f7(double* nocapture readonly %p, double* nocapture %q) #0 {
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entry:
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%0 = load double, double* %p, align 8
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%arrayidx1 = getelementptr inbounds double, double* %p, i64 1
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%1 = load double, double* %arrayidx1, align 8
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%arrayidx2 = getelementptr inbounds double, double* %p, i64 2
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%2 = load double, double* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds double, double* %p, i64 3
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%3 = load double, double* %arrayidx3, align 8
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%arrayidx4 = getelementptr inbounds double, double* %p, i64 4
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%4 = load double, double* %arrayidx4, align 8
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%mul = fmul fast double %0, %1
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%add = fadd fast double %mul, %4
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%mul5 = fmul fast double %1, %2
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%add6 = fadd fast double %mul5, %add
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%mul7 = fmul fast double %1, %3
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%sub = fsub fast double %add6, %mul7
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%mul8 = fmul fast double %2, %3
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%add9 = fadd fast double %mul8, %sub
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%add10 = fadd fast double %add9, %add9
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call void @hhh(double 0.0, double %add10)
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ret void
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}
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declare void @hhh(double, double)
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" }
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attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" }
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attributes #2 = { nounwind }
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