151 lines
5.7 KiB
LLVM
151 lines
5.7 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s
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; Test ldr clustering.
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldr_int:BB#0
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; CHECK: Cluster ld/st SU(1) - SU(2)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldr_int:BB#0
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; EXYNOS: Cluster ld/st SU(1) - SU(2)
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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define i32 @ldr_int(i32* %a) nounwind {
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%p1 = getelementptr inbounds i32, i32* %a, i32 1
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%tmp1 = load i32, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %a, i32 2
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%tmp2 = load i32, i32* %p2, align 2
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%tmp3 = add i32 %tmp1, %tmp2
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ret i32 %tmp3
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}
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; Test ldpsw clustering
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldp_sext_int:BB#0
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; CHECK: Cluster ld/st SU(1) - SU(2)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldp_sext_int:BB#0
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; EXYNOS: Cluster ld/st SU(1) - SU(2)
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
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define i64 @ldp_sext_int(i32* %p) nounwind {
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%tmp = load i32, i32* %p, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp1 = load i32, i32* %add.ptr, align 4
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%sexttmp = sext i32 %tmp to i64
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%sexttmp1 = sext i32 %tmp1 to i64
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%add = add nsw i64 %sexttmp1, %sexttmp
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ret i64 %add
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}
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; Test ldur clustering.
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldur_int:BB#0
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; CHECK: Cluster ld/st SU(2) - SU(1)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDURWi
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDURWi
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldur_int:BB#0
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; EXYNOS: Cluster ld/st SU(2) - SU(1)
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDURWi
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDURWi
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define i32 @ldur_int(i32* %a) nounwind {
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%p1 = getelementptr inbounds i32, i32* %a, i32 -1
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%tmp1 = load i32, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %a, i32 -2
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%tmp2 = load i32, i32* %p2, align 2
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%tmp3 = add i32 %tmp1, %tmp2
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ret i32 %tmp3
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}
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; Test sext + zext clustering.
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldp_half_sext_zext_int:BB#0
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; CHECK: Cluster ld/st SU(3) - SU(4)
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; CHECK: SU(3): %vreg{{[0-9]+}}<def> = LDRSWui
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; CHECK: SU(4): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
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; EXYNOS: Cluster ld/st SU(3) - SU(4)
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; EXYNOS: SU(3): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: SU(4): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
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%tmp0 = load i64, i64* %q, align 4
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%tmp = load i32, i32* %p, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp1 = load i32, i32* %add.ptr, align 4
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%sexttmp = sext i32 %tmp to i64
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%sexttmp1 = zext i32 %tmp1 to i64
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%add = add nsw i64 %sexttmp1, %sexttmp
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%add1 = add nsw i64 %add, %tmp0
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ret i64 %add1
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}
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; Test zext + sext clustering.
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldp_half_zext_sext_int:BB#0
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; CHECK: Cluster ld/st SU(3) - SU(4)
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; CHECK: SU(3): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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; CHECK: SU(4): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
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; EXYNOS: Cluster ld/st SU(3) - SU(4)
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; EXYNOS: SU(3): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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; EXYNOS: SU(4): %vreg{{[0-9]+}}<def> = LDRSWui
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define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
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%tmp0 = load i64, i64* %q, align 4
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%tmp = load i32, i32* %p, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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%tmp1 = load i32, i32* %add.ptr, align 4
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%sexttmp = zext i32 %tmp to i64
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%sexttmp1 = sext i32 %tmp1 to i64
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%add = add nsw i64 %sexttmp1, %sexttmp
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%add1 = add nsw i64 %add, %tmp0
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ret i64 %add1
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}
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; Verify we don't cluster volatile loads.
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldr_int_volatile:BB#0
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; CHECK-NOT: Cluster ld/st
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldr_int_volatile:BB#0
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; EXYNOS-NOT: Cluster ld/st
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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define i32 @ldr_int_volatile(i32* %a) nounwind {
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%p1 = getelementptr inbounds i32, i32* %a, i32 1
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%tmp1 = load volatile i32, i32* %p1, align 2
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%p2 = getelementptr inbounds i32, i32* %a, i32 2
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%tmp2 = load volatile i32, i32* %p2, align 2
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%tmp3 = add i32 %tmp1, %tmp2
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ret i32 %tmp3
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}
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; Test ldq clustering (no clustering for Exynos).
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldq_cluster:BB#0
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; CHECK: Cluster ld/st SU(1) - SU(3)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRQui
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; CHECK: SU(3): %vreg{{[0-9]+}}<def> = LDRQui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldq_cluster:BB#0
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; EXYNOS-NOT: Cluster ld/st
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define <2 x i64> @ldq_cluster(i64* %p) {
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%a1 = bitcast i64* %p to <2 x i64>*
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%tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
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%add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
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%a2 = bitcast i64* %add.ptr2 to <2 x i64>*
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%tmp2 = add nsw <2 x i64> %tmp1, %tmp1
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%tmp3 = load <2 x i64>, <2 x i64>* %a2, align 8
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%res = mul nsw <2 x i64> %tmp2, %tmp3
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ret <2 x i64> %res
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}
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