45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
; RUN: llc -mcpu=cyclone -debug-only=misched < %s 2>&1 | FileCheck %s
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; REQUIRES: asserts
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios7.0.0"
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define void @caller2(i8* %a0, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9) {
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entry:
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tail call void @callee2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a0)
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ret void
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}
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declare void @callee2(i8*, i8*, i8*, i8*, i8*,
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i8*, i8*, i8*, i8*, i8*)
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; Make sure there is a dependence between the load and store to the same stack
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; location during a tail call. Tail calls clobber the incoming argument area and
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; therefore it is not safe to assume argument locations are invariant.
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; PR23459 has a test case that we where miscompiling because of this at the
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; time.
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; CHECK: Frame Objects
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; CHECK: fi#-4: {{.*}} fixed, at location [SP+8]
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; CHECK: fi#-3: {{.*}} fixed, at location [SP]
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; CHECK: fi#-2: {{.*}} fixed, at location [SP+8]
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; CHECK: fi#-1: {{.*}} fixed, at location [SP]
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; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
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; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
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; CHECK: STRXui %vreg{{.*}}, <fi#-4>
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; CHECK: STRXui [[VRB]], <fi#-3>
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; Make sure that there is an dependence edge between fi#-2 and fi#-4.
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; Without this edge the scheduler would be free to move the store accross the load.
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; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2>
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; CHECK-NOT: SU
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; CHECK: Successors:
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; CHECK: ch SU([[DEPSTOREB:.*]]): Latency=0
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; CHECK: ch SU([[DEPSTOREA:.*]]): Latency=0
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; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
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; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>
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