370 lines
17 KiB
C++
370 lines
17 KiB
C++
// Copyright 2021 Google LLC
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//
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// This source code is licensed under the BSD-style license found in the
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// LICENSE file in the root directory of this source tree.
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#include <algorithm>
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#include <cmath>
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#include <functional>
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#include <random>
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#include <vector>
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#include <xnnpack.h>
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#include <benchmark/benchmark.h>
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#include "bench/end2end.h"
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#include "bench/utils.h"
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#include "models/models.h"
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#include <xnnpack/dwconv.h>
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#include <xnnpack/params.h>
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#include <xnnpack/params-init.h>
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static void DWConvEnd2EndBenchmark(
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benchmark::State& state,
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models::ExecutionPlanFactory model_factory,
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xnn_qu8_dwconv_minmax_unipass_ukernel_function dwconv,
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xnn_init_qu8_conv_minmax_params_fn init_params,
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uint8_t channel_tile, uint8_t primary_tile,
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benchmark::utils::IsaCheckFunction isa_check = nullptr)
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{
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if (isa_check && !isa_check(state)) {
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return;
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}
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if (xnn_initialize(nullptr /* allocator */) != xnn_status_success) {
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state.SkipWithError("failed to initialize XNNPACK");
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return;
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}
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// Override microkernels chosen in xnn_initialize
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for (size_t i = 0; i < XNN_MAX_QU8_DWCONV_UKERNELS; i++) {
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// Replace only the microkernel the matching kernel size.
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if (xnn_params.qu8.dwconv[i].primary_tile == primary_tile) {
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// Note: do not directly assign to xnn_params.qu8.dwconv[i] because it breaks older gcc.
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xnn_params.qu8.dwconv[i].minmax.unipass = xnn_dwconv_unipass_ukernel_function(dwconv);
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xnn_params.qu8.dwconv[i].channel_tile = channel_tile;
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xnn_params.qu8.dwconv[i].primary_tile = primary_tile;
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xnn_params.qu8.dwconv[i].incremental_tile = 0;
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xnn_params.qu8.dwconv[i].init.qu8 = init_params;
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break;
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}
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}
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auto execution_plan = model_factory(nullptr);
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if (execution_plan.empty()) {
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state.SkipWithError("failed to create a model");
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return;
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}
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for (auto _ : state) {
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for (const std::unique_ptr<xnn_operator, decltype(&xnn_delete_operator)>& op : execution_plan) {
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xnn_status status = xnn_run_operator(op.get(), nullptr);
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if (status != xnn_status_success) {
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state.SkipWithError("failed to run a model");
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return;
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}
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}
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}
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const uint64_t cpu_frequency = benchmark::utils::GetCurrentCpuFrequency();
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if (cpu_frequency != 0) {
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state.counters["cpufreq"] = cpu_frequency;
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}
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}
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#if XNN_ARCH_ARM || XNN_ARCH_ARM64
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static void qu8_dwconv_up8x9__neon_mul8(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul8,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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8 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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static void qu8_dwconv_up16x9__neon_mul8(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul8,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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static void qu8_dwconv_up24x9__neon_mul8(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul8,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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24 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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static void qu8_dwconv_up32x9__neon_mul8(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul8,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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32 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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static void qu8_dwconv_up8x9__neon_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up8x9__neon_mul16,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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8 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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static void qu8_dwconv_up16x9__neon_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up16x9__neon_mul16,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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static void qu8_dwconv_up24x9__neon_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up24x9__neon_mul16,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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24 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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static void qu8_dwconv_up32x9__neon_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_rndnu_ukernel_up32x9__neon_mul16,
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xnn_init_qu8_conv_minmax_rndnu_neon_params,
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32 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckNEON);
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}
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__neon_mul8);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__neon_mul8);
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BENCHMARK_QU8_END2END(qu8_dwconv_up24x9__neon_mul8);
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BENCHMARK_QU8_END2END(qu8_dwconv_up32x9__neon_mul8);
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__neon_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__neon_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up24x9__neon_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up32x9__neon_mul16);
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#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
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#if XNN_ARCH_X86 || XNN_ARCH_X86_64
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static void qu8_dwconv_up16x9__avx512skx_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx512skx_mul32,
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xnn_init_qu8_conv_minmax_fp32_avx512_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX512SKX);
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}
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static void qu8_dwconv_up32x9__avx512skx_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up32x9__avx512skx_mul32,
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xnn_init_qu8_conv_minmax_fp32_avx512_params,
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32 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX512SKX);
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}
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static void qu8_dwconv_up8x9__avx2_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__avx2_mul32,
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xnn_init_qu8_conv_minmax_fp32_avx2_params,
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8 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX2);
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}
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static void qu8_dwconv_up16x9__avx2_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx2_mul32,
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xnn_init_qu8_conv_minmax_fp32_avx2_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX2);
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}
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static void qu8_dwconv_up32x9__avx2_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up32x9__avx2_mul32,
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xnn_init_qu8_conv_minmax_fp32_avx2_params,
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32 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX2);
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}
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static void qu8_dwconv_up8x9__avx_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__avx_mul16,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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8 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX);
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}
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static void qu8_dwconv_up16x9__avx_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx_mul16,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX);
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}
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static void qu8_dwconv_up8x9__avx_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__avx_mul32,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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8 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX);
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}
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static void qu8_dwconv_up16x9__avx_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx_mul32,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckAVX);
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}
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static void qu8_dwconv_up8x9__sse41_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__sse41_mul16,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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8 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckSSE41);
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}
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static void qu8_dwconv_up16x9__sse41_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__sse41_mul16,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckSSE41);
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}
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static void qu8_dwconv_up8x9__sse41_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__sse41_mul32,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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8 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckSSE41);
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}
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static void qu8_dwconv_up16x9__sse41_mul32(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__sse41_mul32,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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16 /* channel tile */, 9 /* primary tile */, benchmark::utils::CheckSSE41);
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}
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static void qu8_dwconv_up8x9__sse2_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__sse2_mul16,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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8 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up16x9__sse2_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__sse2_mul16,
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xnn_init_qu8_conv_minmax_fp32_sse2_params,
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16 /* channel tile */, 9 /* primary tile */);
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}
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__avx512skx_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up32x9__avx512skx_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__avx2_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__avx2_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up32x9__avx2_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__avx_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__avx_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__avx_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__avx_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__sse41_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__sse41_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__sse41_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__sse41_mul32);
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__sse2_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__sse2_mul16);
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#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
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#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
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static void qu8_dwconv_up8x9__wasmsimd_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__wasmsimd_mul16,
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xnn_init_qu8_conv_minmax_fp32_wasmsimd_params,
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8 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up16x9__wasmsimd_mul16(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__wasmsimd_mul16,
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xnn_init_qu8_conv_minmax_fp32_wasmsimd_params,
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16 /* channel tile */, 9 /* primary tile */);
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}
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BENCHMARK_QU8_END2END(qu8_dwconv_up8x9__wasmsimd_mul16);
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BENCHMARK_QU8_END2END(qu8_dwconv_up16x9__wasmsimd_mul16);
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#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
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#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
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static void qu8_dwconv_up1x9__wasm_fmagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up1x9__wasm_fmagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_fmagic_params,
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1 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up2x9__wasm_fmagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up2x9__wasm_fmagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_fmagic_params,
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2 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up4x9__wasm_fmagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up4x9__wasm_fmagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_fmagic_params,
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4 /* channel tile */, 9 /* primary tile */);
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}
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BENCHMARK_QU8_END2END(qu8_dwconv_up1x9__wasm_fmagic);
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BENCHMARK_QU8_END2END(qu8_dwconv_up2x9__wasm_fmagic);
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BENCHMARK_QU8_END2END(qu8_dwconv_up4x9__wasm_fmagic);
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#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
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static void qu8_dwconv_up1x9__scalar_fmagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up1x9__scalar_fmagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_fmagic_params,
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1 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up2x9__scalar_fmagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up2x9__scalar_fmagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_fmagic_params,
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2 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up4x9__scalar_fmagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up4x9__scalar_fmagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_fmagic_params,
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4 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up1x9__scalar_imagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up1x9__scalar_imagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_imagic_params,
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1 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up2x9__scalar_imagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
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xnn_qu8_dwconv_minmax_fp32_ukernel_up2x9__scalar_imagic,
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xnn_init_qu8_conv_minmax_fp32_scalar_imagic_params,
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2 /* channel tile */, 9 /* primary tile */);
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}
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static void qu8_dwconv_up4x9__scalar_imagic(benchmark::State& state, models::ExecutionPlanFactory model) {
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DWConvEnd2EndBenchmark(state, model,
|
|
xnn_qu8_dwconv_minmax_fp32_ukernel_up4x9__scalar_imagic,
|
|
xnn_init_qu8_conv_minmax_fp32_scalar_imagic_params,
|
|
4 /* channel tile */, 9 /* primary tile */);
|
|
}
|
|
|
|
static void qu8_dwconv_up1x9__scalar_lrintf(benchmark::State& state, models::ExecutionPlanFactory model) {
|
|
DWConvEnd2EndBenchmark(state, model,
|
|
xnn_qu8_dwconv_minmax_fp32_ukernel_up1x9__scalar_lrintf,
|
|
xnn_init_qu8_conv_minmax_fp32_scalar_lrintf_params,
|
|
1 /* channel tile */, 9 /* primary tile */);
|
|
}
|
|
static void qu8_dwconv_up2x9__scalar_lrintf(benchmark::State& state, models::ExecutionPlanFactory model) {
|
|
DWConvEnd2EndBenchmark(state, model,
|
|
xnn_qu8_dwconv_minmax_fp32_ukernel_up2x9__scalar_lrintf,
|
|
xnn_init_qu8_conv_minmax_fp32_scalar_lrintf_params,
|
|
2 /* channel tile */, 9 /* primary tile */);
|
|
}
|
|
static void qu8_dwconv_up4x9__scalar_lrintf(benchmark::State& state, models::ExecutionPlanFactory model) {
|
|
DWConvEnd2EndBenchmark(state, model,
|
|
xnn_qu8_dwconv_minmax_fp32_ukernel_up4x9__scalar_lrintf,
|
|
xnn_init_qu8_conv_minmax_fp32_scalar_lrintf_params,
|
|
4 /* channel tile */, 9 /* primary tile */);
|
|
}
|
|
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up1x9__scalar_fmagic);
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up2x9__scalar_fmagic);
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up4x9__scalar_fmagic);
|
|
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up1x9__scalar_imagic);
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up2x9__scalar_imagic);
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up4x9__scalar_imagic);
|
|
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up1x9__scalar_lrintf);
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up2x9__scalar_lrintf);
|
|
BENCHMARK_QU8_END2END(qu8_dwconv_up4x9__scalar_lrintf);
|
|
|
|
|
|
#ifndef XNNPACK_BENCHMARK_NO_MAIN
|
|
BENCHMARK_MAIN();
|
|
#endif
|