385 lines
12 KiB
ArmAsm
385 lines
12 KiB
ArmAsm
///*****************************************************************************
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//*
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//* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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//*
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//* Licensed under the Apache License, Version 2.0 (the "License");
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//* you may not use this file except in compliance with the License.
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//* You may obtain a copy of the License at:
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//*
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//* http://www.apache.org/licenses/LICENSE-2.0
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//*
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//* Unless required by applicable law or agreed to in writing, software
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//* distributed under the License is distributed on an "AS IS" BASIS,
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//* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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//* See the License for the specific language governing permissions and
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//* limitations under the License.
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//*
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//*****************************************************************************/
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///**
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//*******************************************************************************
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//* @file
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//* ihevc_intra_pred_filters_planar.s
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//*
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//* @brief
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//* contains function definitions for inter prediction interpolation.
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//* functions are coded using neon intrinsics and can be compiled using
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//* rvct
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//*
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//* @author
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//* akshaya mukund
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//*
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//* @par list of functions:
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//*
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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///**
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//*******************************************************************************
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//*
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//* @brief
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//* luma intraprediction filter for planar input
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//*
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//* @par description:
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//*
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//* @param[in] pu1_ref
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//* uword8 pointer to the source
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//*
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//* @param[out] pu1_dst
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//* uword8 pointer to the destination
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//*
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//* @param[in] src_strd
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//* integer source stride
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//*
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//* @param[in] dst_strd
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//* integer destination stride
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//*
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//* @param[in] pi1_coeff
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//* word8 pointer to the planar coefficients
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//*
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//* @param[in] nt
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//* size of tranform block
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//*
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//* @param[in] mode
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//* type of filtering
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//*
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//* @returns
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//*
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//* @remarks
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//* none
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//*
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//*******************************************************************************
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//*/
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//void ihevc_intra_pred_luma_planar(uword8* pu1_ref,
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// word32 src_strd,
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// uword8* pu1_dst,
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// word32 dst_strd,
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// word32 nt,
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// word32 mode,
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// word32 pi1_coeff)
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//**************variables vs registers*****************************************
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//x0 => *pu1_ref
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//x1 => src_strd
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//x2 => *pu1_dst
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//x3 => dst_strd
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//stack contents from #40
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// nt
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// mode
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// pi1_coeff
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.text
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.align 4
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.include "ihevc_neon_macros.s"
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.globl ihevc_intra_pred_chroma_planar_av8
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.extern gau1_ihevc_planar_factor
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.type ihevc_intra_pred_chroma_planar_av8, %function
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ihevc_intra_pred_chroma_planar_av8:
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// stmfd sp!, {x4-x12, x14} //stack stores the values of the arguments
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stp d10,d11,[sp,#-16]!
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stp d12,d13,[sp,#-16]!
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stp d8,d14,[sp,#-16]! // Storing d14 using { sub sp,sp,#8; str d14,[sp] } is giving bus error.
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// d8 is used as dummy register and stored along with d14 using stp. d8 is not used in the function.
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stp x19, x20,[sp,#-16]!
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adrp x11, :got:gau1_ihevc_planar_factor //loads table of coeffs
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ldr x11, [x11, #:got_lo12:gau1_ihevc_planar_factor]
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clz w5,w4
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sub x20, x5, #32
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neg x5, x20
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dup v14.8h,w5
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neg v14.8h, v14.8h //shr value (so vneg)
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dup v2.8b,w4 //nt
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dup v16.8h,w4 //nt
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sub x6, x4, #1 //nt-1
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add x6, x0,x6,lsl #1 //2*(nt-1)
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ldr w7, [x6]
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sxtw x7,w7
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dup v0.4h,w7 //src[nt-1]
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add x6, x4, x4,lsl #1 //3nt
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add x6, x6, #1 //3nt + 1
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lsl x6,x6,#1 //2*(3nt + 1)
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add x6, x6, x0
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ldr w7, [x6]
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sxtw x7,w7
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dup v1.4h,w7 //src[3nt+1]
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add x6, x4, x4 //2nt
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add x14, x6, #1 //2nt+1
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lsl x14,x14,#1 //2*(2nt+1)
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sub x6, x6, #1 //2nt-1
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lsl x6,x6,#1 //2*(2nt-1)
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add x6, x6, x0 //&src[2nt-1]
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add x14, x14, x0 //&src[2nt+1]
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mov x8, #1 //row+1 (row is first 0)
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sub x9, x4, x8 //nt-1-row (row is first 0)
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dup v5.8b,w8 //row + 1
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dup v6.8b,w9 //nt - 1 - row
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mov v7.8b, v5.8b //mov #1 to d7 to used for inc for row+1 and dec for nt-1-row
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add x12, x11, #1 //coeffs (to be reloaded after every row)
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mov x1, x4 //nt (row counter) (dec after every row)
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mov x5, x2 //dst (to be reloaded after every row and inc by dst_strd)
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mov x10, #8 //increment for the coeffs
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mov x0, x14 //&src[2nt+1] (to be reloaded after every row)
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cmp x4, #4
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beq tf_sz_4
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mov x10,x6
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tf_sz_8_16:
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ld1 {v10.8b, v11.8b}, [x14],#16 //load src[2nt+1+col]
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ld1 {v17.8b},[x12],#8
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mov v25.8b, v17.8b
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zip1 v29.8b, v17.8b, v25.8b
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zip2 v25.8b, v17.8b, v25.8b
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mov v17.d[0], v29.d[0]
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sub v30.8b, v2.8b , v17.8b //[nt-1-col]
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sub v31.8b, v2.8b , v25.8b
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loop_sz_8_16:
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ldr w7, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
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sxtw x7,w7
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umull v12.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
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ldr w11, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
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sxtw x11,w11
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umlal v12.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
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dup v4.4h,w7 //src[2nt-1-row]
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umlal v12.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
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dup v3.4h,w11 //src[2nt-1-row]
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umlal v12.8h, v30.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
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umull v28.8h, v5.8b, v0.8b
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ldr w7, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
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sxtw x7,w7
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umlal v28.8h, v6.8b, v11.8b
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add v18.8b, v5.8b , v7.8b //row++ [(row+1)++]c
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umlal v28.8h, v31.8b, v4.8b
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sub v19.8b, v6.8b , v7.8b //[nt-1-row]--
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umlal v28.8h, v25.8b, v1.8b
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dup v4.4h,w7 //src[2nt-1-row]
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umull v26.8h, v18.8b, v0.8b //(row+1) * src[nt-1]
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add v12.8h, v12.8h , v16.8h //add (nt)
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umlal v26.8h, v19.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
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sshl v12.8h, v12.8h, v14.8h //shr
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umlal v26.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
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add v28.8h, v28.8h , v16.8h
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umlal v26.8h, v30.8b, v3.8b //(nt-1-col) * src[2nt-1-row]
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sshl v28.8h, v28.8h, v14.8h
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umull v24.8h, v18.8b, v0.8b
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add v5.8b, v18.8b , v7.8b //row++ [(row+1)++]
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umlal v24.8h, v19.8b, v11.8b
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sub v6.8b, v19.8b , v7.8b //[nt-1-row]--
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umlal v24.8h, v25.8b, v1.8b
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xtn v12.8b, v12.8h
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umlal v24.8h, v31.8b, v3.8b
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xtn v13.8b, v28.8h
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add v26.8h, v26.8h , v16.8h //add (nt)
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umull v22.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
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sshl v26.8h, v26.8h, v14.8h //shr
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umlal v22.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
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st1 {v12.2s, v13.2s}, [x2], x3
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umlal v22.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
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add v24.8h, v24.8h , v16.8h
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umlal v22.8h, v30.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
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sshl v24.8h, v24.8h, v14.8h
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umull v20.8h, v5.8b, v0.8b
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add v18.8b, v5.8b , v7.8b //row++ [(row+1)++]c
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umlal v20.8h, v6.8b, v11.8b
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sub v19.8b, v6.8b , v7.8b //[nt-1-row]--
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umlal v20.8h, v31.8b, v4.8b
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ldr w11, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
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sxtw x11,w11
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umlal v20.8h, v25.8b, v1.8b
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dup v3.4h,w11 //src[2nt-1-row]
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add v22.8h, v22.8h , v16.8h //add (nt)
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umull v12.8h, v18.8b, v0.8b //(row+1) * src[nt-1]
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xtn v26.8b, v26.8h
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umlal v12.8h, v19.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
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xtn v27.8b, v24.8h
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umlal v12.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
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sshl v22.8h, v22.8h, v14.8h //shr
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umlal v12.8h, v30.8b, v3.8b //(nt-1-col) * src[2nt-1-row]
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add v20.8h, v20.8h , v16.8h
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umull v28.8h, v18.8b, v0.8b
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st1 {v26.2s, v27.2s}, [x2], x3
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umlal v28.8h, v19.8b, v11.8b
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add v5.8b, v18.8b , v7.8b //row++ [(row+1)++]
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sub v6.8b, v19.8b , v7.8b //[nt-1-row]--
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umlal v28.8h, v25.8b, v1.8b
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umlal v28.8h, v31.8b, v3.8b
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sshl v20.8h, v20.8h, v14.8h
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add v12.8h, v12.8h , v16.8h //add (nt)
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xtn v22.8b, v22.8h
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add v28.8h, v28.8h , v16.8h
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xtn v23.8b, v20.8h
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sshl v12.8h, v12.8h, v14.8h //shr
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st1 {v22.2s, v23.2s}, [x2], x3
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sshl v28.8h, v28.8h, v14.8h
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xtn v20.8b, v12.8h
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xtn v21.8b, v28.8h
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st1 {v20.2s, v21.2s}, [x2], x3
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subs x1, x1, #4
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bne loop_sz_8_16
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cmp x4,#16
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bne end_loop
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sub x4, x4,#16
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dup v5.8b,w8 //row + 1
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dup v6.8b,w9 //nt - 1 - row
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mov v7.8b, v5.8b //mov #1 to d7 to used for inc for row+1 and dec for nt-1-row
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mov x6,x10
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mov x1,#16
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sub x2,x2,x3,lsl #4
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add x2,x2,#16
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ld1 {v10.8b, v11.8b}, [x14],#16 //load src[2nt+1+col]
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ld1 {v17.8b},[x12],#8
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mov v25.8b, v17.8b
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zip1 v29.8b, v17.8b, v25.8b
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zip2 v25.8b, v17.8b, v25.8b
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mov v17.d[0], v29.d[0]
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sub v30.8b, v2.8b , v17.8b //[nt-1-col]
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sub v31.8b, v2.8b , v25.8b
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beq loop_sz_8_16
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tf_sz_4:
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ld1 {v10.8b},[x14] //load src[2nt+1+col]
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ld1 {v17.8b},[x12], x10 //load 8 coeffs [col+1]
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mov v25.8b, v17.8b
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zip1 v29.8b, v17.8b, v25.8b
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zip2 v25.8b, v17.8b, v25.8b
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mov v17.d[0], v29.d[0]
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loop_sz_4:
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//mov x10, #4 @reduce inc to #4 for 4x4
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ldr w7, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
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sxtw x7,w7
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dup v4.4h,w7 //src[2nt-1-row]
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sub v25.8b, v2.8b , v17.8b //[nt-1-col]
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umull v12.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
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umlal v12.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
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umlal v12.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
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umlal v12.8h, v25.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
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// vadd.i16 q6, q6, q8 @add (nt)
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// vshl.s16 q6, q6, q7 @shr
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// vmovn.i16 d12, q6
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rshrn v12.8b, v12.8h,#3
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st1 {v12.2s},[x2], x3
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add v5.8b, v5.8b , v7.8b //row++ [(row+1)++]
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sub v6.8b, v6.8b , v7.8b //[nt-1-row]--
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subs x1, x1, #1
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bne loop_sz_4
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end_loop:
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// ldmfd sp!,{x4-x12,x15} //reload the registers from sp
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ldp x19, x20,[sp],#16
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ldp d8,d14,[sp],#16 // Loading d14 using { ldr d14,[sp]; add sp,sp,#8 } is giving bus error.
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// d8 is used as dummy register and loaded along with d14 using ldp. d8 is not used in the function.
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ldp d12,d13,[sp],#16
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ldp d10,d11,[sp],#16
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ret
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