836 lines
22 KiB
C
836 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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*
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* (C) COPYRIGHT 2014-2023 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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/* AUTOMATICALLY GENERATED FILE. If you want to amend the issues/features,
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* please update base/tools/hwconfig_generator/hwc_{issues,features}.py
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* For more information see base/tools/hwconfig_generator/README
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*/
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#ifndef _BASE_HWCONFIG_ISSUES_H_
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#define _BASE_HWCONFIG_ISSUES_H_
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enum base_hw_issue {
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BASE_HW_ISSUE_5736,
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_T76X_3953,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_7940,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TMIX_8138,
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BASE_HW_ISSUE_TMIX_8206,
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BASE_HW_ISSUE_TMIX_8343,
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BASE_HW_ISSUE_TMIX_8463,
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BASE_HW_ISSUE_TMIX_8456,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TMIX_8438,
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BASE_HW_ISSUE_TNOX_1194,
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BASE_HW_ISSUE_TGOX_R1_1234,
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BASE_HW_ISSUE_TTRX_1337,
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BASE_HW_ISSUE_TSIX_1792,
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BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
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BASE_HW_ISSUE_TTRX_3076,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_TTRX_3414,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TTRX_3083,
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BASE_HW_ISSUE_TTRX_3470,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TTRX_3485,
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BASE_HW_ISSUE_GPU2019_3212,
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BASE_HW_ISSUE_TURSEHW_1997,
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BASE_HW_ISSUE_GPU2019_3878,
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BASE_HW_ISSUE_TURSEHW_2716,
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BASE_HW_ISSUE_GPU2019_3901,
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BASE_HW_ISSUE_GPU2021PRO_290,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_TITANHW_2679,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_generic[] = {
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p0_05dev0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_T76X_3953,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TMIX_8138,
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BASE_HW_ISSUE_TMIX_8206,
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BASE_HW_ISSUE_TMIX_8343,
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BASE_HW_ISSUE_TMIX_8463,
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BASE_HW_ISSUE_TMIX_8456,
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BASE_HW_ISSUE_TMIX_8438,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_7940,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TMIX_8138,
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BASE_HW_ISSUE_TMIX_8206,
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BASE_HW_ISSUE_TMIX_8343,
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BASE_HW_ISSUE_TMIX_8463,
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BASE_HW_ISSUE_TMIX_8456,
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BASE_HW_ISSUE_TMIX_8438,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p1[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_7940,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TMIX_8138,
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BASE_HW_ISSUE_TMIX_8206,
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BASE_HW_ISSUE_TMIX_8343,
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BASE_HW_ISSUE_TMIX_8463,
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BASE_HW_ISSUE_TMIX_8456,
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BASE_HW_ISSUE_TMIX_8438,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tMIx[] = {
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BASE_HW_ISSUE_5736,
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_7940,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TMIX_8138,
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BASE_HW_ISSUE_TMIX_8206,
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BASE_HW_ISSUE_TMIX_8343,
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BASE_HW_ISSUE_TMIX_8456,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p1[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p2[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p3[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_10682,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tHEx[] = {
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BASE_HW_ISSUE_5736,
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_7891,
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BASE_HW_ISSUE_TMIX_8042,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r0p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TSIX_1792,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r0p1[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TSIX_1792,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r1p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_11054,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r1p1[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tSIx[] = {
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BASE_HW_ISSUE_5736,
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tDVx_r0p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tDVx[] = {
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BASE_HW_ISSUE_5736,
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNOx_r0p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TNOX_1194,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_GPU2017_1336,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tNOx[] = {
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BASE_HW_ISSUE_5736,
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGOx_r0p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TNOX_1194,
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BASE_HW_ISSUE_TTRX_921,
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|
BASE_HW_ISSUE_GPU2017_1336,
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|
BASE_HW_ISSUE_TTRX_3464,
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|
BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGOx_r1p0[] = {
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BASE_HW_ISSUE_9435,
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|
BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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|
BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TGOX_R1_1234,
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BASE_HW_ISSUE_TTRX_921,
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|
BASE_HW_ISSUE_GPU2017_1336,
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|
BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tGOx[] = {
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BASE_HW_ISSUE_5736,
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TMIX_8133,
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BASE_HW_ISSUE_TSIX_1116,
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_3464,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p0[] = {
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BASE_HW_ISSUE_9435,
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BASE_HW_ISSUE_TSIX_2033,
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|
BASE_HW_ISSUE_TTRX_1337,
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BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
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|
BASE_HW_ISSUE_TTRX_3076,
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BASE_HW_ISSUE_TTRX_921,
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BASE_HW_ISSUE_TTRX_3414,
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|
BASE_HW_ISSUE_GPU2017_1336,
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|
BASE_HW_ISSUE_TTRX_3083,
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|
BASE_HW_ISSUE_TTRX_3470,
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|
BASE_HW_ISSUE_TTRX_3464,
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|
BASE_HW_ISSUE_TTRX_3485,
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|
BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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|
};
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|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p1[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_3076,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_GPU2017_1336,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TTRX_3485,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p2[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_3076,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_GPU2017_1336,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTRx[] = {
|
|
BASE_HW_ISSUE_5736,
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNAx_r0p0[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_3076,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_GPU2017_1336,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TTRX_3485,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNAx_r0p1[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_3076,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_GPU2017_1336,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tNAx[] = {
|
|
BASE_HW_ISSUE_5736,
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r0p0[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TTRX_3485,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r0p1[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r1p0[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r1p1[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tBEx[] = {
|
|
BASE_HW_ISSUE_5736,
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_lBEx_r1p0[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TTRX_3485,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_lBEx_r1p1[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r0p0[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r1p0[] = {
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
|
|
BASE_HW_ISSUE_TTRX_921,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tBAx[] = {
|
|
BASE_HW_ISSUE_5736,
|
|
BASE_HW_ISSUE_9435,
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TTRX_3414,
|
|
BASE_HW_ISSUE_TTRX_3083,
|
|
BASE_HW_ISSUE_TTRX_3470,
|
|
BASE_HW_ISSUE_TTRX_3464,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tODx_r0p0[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3212,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tODx[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3212,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGRx_r0p0[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tGRx[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tVAx_r0p0[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tVAx[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r0p0[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TURSEHW_1997,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_TURSEHW_2716,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_GPU2021PRO_290,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_TITANHW_2679,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r0p1[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_TURSEHW_1997,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_TURSEHW_2716,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_GPU2021PRO_290,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_TITANHW_2679,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTUx[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_TURSEHW_2716,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_GPU2021PRO_290,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_TITANHW_2679,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p0[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_TURSEHW_2716,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_GPU2021PRO_290,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_TITANHW_2679,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p1[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_TURSEHW_2716,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_GPU2021PRO_290,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_TITANHW_2679,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p2[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
|
|
BASE_HW_ISSUE_TURSEHW_2716,
|
|
BASE_HW_ISSUE_GPU2019_3901,
|
|
BASE_HW_ISSUE_GPU2021PRO_290,
|
|
BASE_HW_ISSUE_TITANHW_2710,
|
|
BASE_HW_ISSUE_TITANHW_2679,
|
|
BASE_HW_ISSUE_GPU2022PRO_148,
|
|
BASE_HW_ISSUE_END
|
|
};
|
|
|
|
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p3[] = {
|
|
BASE_HW_ISSUE_TSIX_2033,
|
|
BASE_HW_ISSUE_TTRX_1337,
|
|
BASE_HW_ISSUE_GPU2019_3878,
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BASE_HW_ISSUE_TURSEHW_2716,
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BASE_HW_ISSUE_GPU2019_3901,
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BASE_HW_ISSUE_GPU2021PRO_290,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_TITANHW_2679,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTIx[] = {
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_1337,
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BASE_HW_ISSUE_TURSEHW_2716,
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BASE_HW_ISSUE_GPU2021PRO_290,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_TITANHW_2679,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTIx_r0p0[] = {
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BASE_HW_ISSUE_TSIX_2033,
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BASE_HW_ISSUE_TTRX_1337,
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BASE_HW_ISSUE_TURSEHW_2716,
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BASE_HW_ISSUE_GPU2021PRO_290,
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BASE_HW_ISSUE_TITANHW_2710,
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BASE_HW_ISSUE_TITANHW_2679,
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BASE_HW_ISSUE_GPU2022PRO_148,
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BASE_HW_ISSUE_END
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};
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#endif /* _BASE_HWCONFIG_ISSUES_H_ */
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