1313 lines
36 KiB
C
1313 lines
36 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip PIPE USB3.0 PCIE SATA combphy driver
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*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <dt-bindings/phy/phy.h>
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#define BIT_WRITEABLE_SHIFT 16
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struct rockchip_combphy_priv;
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struct combphy_reg {
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u32 offset;
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u16 bitend;
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u16 bitstart;
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u16 disable;
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u16 enable;
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};
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struct rockchip_combphy_grfcfg {
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struct combphy_reg pcie_mode_set;
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struct combphy_reg usb_mode_set;
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struct combphy_reg sgmii_mode_set;
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struct combphy_reg qsgmii_mode_set;
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struct combphy_reg pipe_rxterm_set;
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struct combphy_reg pipe_txelec_set;
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struct combphy_reg pipe_txcomp_set;
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struct combphy_reg pipe_clk_24m;
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struct combphy_reg pipe_clk_25m;
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struct combphy_reg pipe_clk_100m;
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struct combphy_reg pipe_phymode_sel;
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struct combphy_reg pipe_rate_sel;
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struct combphy_reg pipe_rxterm_sel;
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struct combphy_reg pipe_txelec_sel;
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struct combphy_reg pipe_txcomp_sel;
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struct combphy_reg pipe_clk_ext;
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struct combphy_reg pipe_sel_usb;
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struct combphy_reg pipe_sel_qsgmii;
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struct combphy_reg pipe_phy_status;
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struct combphy_reg con0_for_pcie;
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struct combphy_reg con1_for_pcie;
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struct combphy_reg con2_for_pcie;
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struct combphy_reg con3_for_pcie;
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struct combphy_reg con0_for_sata;
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struct combphy_reg con1_for_sata;
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struct combphy_reg con2_for_sata;
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struct combphy_reg con3_for_sata;
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struct combphy_reg pipe_con0_for_sata;
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struct combphy_reg pipe_con1_for_sata;
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struct combphy_reg pipe_sgmii_mac_sel;
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struct combphy_reg pipe_xpcs_phy_ready;
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struct combphy_reg u3otg0_port_en;
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struct combphy_reg u3otg1_port_en;
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struct combphy_reg pipe_phy_grf_reset;
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};
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struct rockchip_combphy_cfg {
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const int num_clks;
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const struct clk_bulk_data *clks;
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const struct rockchip_combphy_grfcfg *grfcfg;
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bool force_det_out; /* Tx detect Rx errata */
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int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
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};
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struct rockchip_combphy_priv {
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u8 mode;
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void __iomem *mmio;
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int num_clks;
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struct clk_bulk_data *clks;
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struct device *dev;
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struct regmap *pipe_grf;
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struct regmap *phy_grf;
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struct phy *phy;
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struct reset_control *apb_rst;
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struct reset_control *phy_rst;
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const struct rockchip_combphy_cfg *cfg;
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};
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static inline bool param_read(struct regmap *base,
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const struct combphy_reg *reg, u32 val)
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{
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int ret;
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u32 mask, orig, tmp;
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ret = regmap_read(base, reg->offset, &orig);
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if (ret)
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return false;
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mask = GENMASK(reg->bitend, reg->bitstart);
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tmp = (orig & mask) >> reg->bitstart;
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return tmp == val;
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}
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static int param_write(struct regmap *base,
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const struct combphy_reg *reg, bool en)
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{
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u32 val, mask, tmp;
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tmp = en ? reg->enable : reg->disable;
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
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return regmap_write(base, reg->offset, val);
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}
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static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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u32 mask, val;
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mask = GENMASK(cfg->pipe_phy_status.bitend,
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cfg->pipe_phy_status.bitstart);
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regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
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val = (val & mask) >> cfg->pipe_phy_status.bitstart;
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return val;
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}
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static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
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{
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int ret = 0;
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u32 val;
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for pcie\n");
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return ret;
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}
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}
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if (priv->cfg->force_det_out) {
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val = readl(priv->mmio + (0x19 << 2));
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val |= BIT(5);
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writel(val, priv->mmio + (0x19 << 2));
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}
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return ret;
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}
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static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
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int ret = 0;
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if (device_property_present(priv->dev, "rockchip,dis-u3otg0-port")) {
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ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
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false);
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return ret;
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} else if (device_property_present(priv->dev, "rockchip,dis-u3otg1-port")) {
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ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
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false);
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return ret;
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}
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for usb3\n");
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return ret;
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}
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}
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return ret;
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}
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static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
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{
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int ret = 0;
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for sata\n");
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return ret;
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}
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}
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return ret;
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}
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static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
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{
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int ret = 0;
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if (priv->cfg->combphy_cfg) {
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ret = priv->cfg->combphy_cfg(priv);
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if (ret) {
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dev_err(priv->dev, "failed to init phy for sgmii\n");
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return ret;
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}
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}
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return ret;
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}
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static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
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{
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switch (priv->mode) {
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case PHY_TYPE_PCIE:
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rockchip_combphy_pcie_init(priv);
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break;
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case PHY_TYPE_USB3:
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rockchip_combphy_usb3_init(priv);
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break;
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case PHY_TYPE_SATA:
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rockchip_combphy_sata_init(priv);
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break;
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case PHY_TYPE_SGMII:
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case PHY_TYPE_QSGMII:
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return rockchip_combphy_sgmii_init(priv);
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default:
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dev_err(priv->dev, "incompatible PHY type\n");
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return -EINVAL;
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}
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return 0;
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}
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static int rockchip_combphy_init(struct phy *phy)
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{
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struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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u32 val;
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int ret;
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ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
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if (ret) {
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dev_err(priv->dev, "failed to enable clks\n");
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return ret;
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}
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ret = rockchip_combphy_set_mode(priv);
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if (ret)
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goto err_clk;
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ret = reset_control_deassert(priv->phy_rst);
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if (ret)
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goto err_clk;
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if (cfg->pipe_phy_grf_reset.enable)
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param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
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if (priv->mode == PHY_TYPE_USB3) {
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ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
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priv, val,
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val == cfg->pipe_phy_status.enable,
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10, 1000);
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if (ret)
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dev_warn(priv->dev, "wait phy status ready timeout\n");
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}
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return 0;
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err_clk:
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clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
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return ret;
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}
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static int rockchip_combphy_exit(struct phy *phy)
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{
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struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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if (cfg->pipe_phy_grf_reset.enable)
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param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
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clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
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reset_control_assert(priv->phy_rst);
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return 0;
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}
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static const struct phy_ops rochchip_combphy_ops = {
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.init = rockchip_combphy_init,
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.exit = rockchip_combphy_exit,
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.owner = THIS_MODULE,
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};
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static struct phy *rockchip_combphy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
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if (args->args_count != 1) {
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dev_err(dev, "invalid number of arguments\n");
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return ERR_PTR(-EINVAL);
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}
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if (priv->mode != PHY_NONE && priv->mode != args->args[0])
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dev_warn(dev, "phy type select %d overwriting type %d\n",
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args->args[0], priv->mode);
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priv->mode = args->args[0];
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return priv->phy;
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}
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static int rockchip_combphy_parse_dt(struct device *dev,
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struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
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int ret, mac_id;
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u32 vals[4];
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ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
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if (ret == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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if (ret)
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priv->num_clks = 0;
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priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,pipe-grf");
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if (IS_ERR(priv->pipe_grf)) {
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dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
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return PTR_ERR(priv->pipe_grf);
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}
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priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,pipe-phy-grf");
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if (IS_ERR(priv->phy_grf)) {
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dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
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return PTR_ERR(priv->phy_grf);
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}
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if (device_property_present(dev, "rockchip,dis-u3otg0-port"))
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param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
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false);
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else if (device_property_present(dev, "rockchip,dis-u3otg1-port"))
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param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
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false);
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if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) &&
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(mac_id > 0))
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param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
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true);
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if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
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vals, ARRAY_SIZE(vals)))
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regmap_write(priv->pipe_grf, vals[0],
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(GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1]));
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priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
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if (IS_ERR(priv->apb_rst)) {
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ret = PTR_ERR(priv->apb_rst);
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if (ret != -EPROBE_DEFER)
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dev_warn(dev, "failed to get apb reset\n");
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return ret;
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}
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priv->phy_rst = devm_reset_control_get_optional(dev, "combphy");
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if (IS_ERR(priv->phy_rst)) {
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ret = PTR_ERR(priv->phy_rst);
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if (ret != -EPROBE_DEFER)
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dev_warn(dev, "failed to get phy reset\n");
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return ret;
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}
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return reset_control_assert(priv->phy_rst);
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}
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static int rockchip_combphy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct rockchip_combphy_priv *priv;
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const struct rockchip_combphy_cfg *phy_cfg;
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struct resource *res;
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int ret;
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phy_cfg = of_device_get_match_data(dev);
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if (!phy_cfg) {
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dev_err(dev, "No OF match data provided\n");
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return -EINVAL;
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}
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->mmio)) {
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ret = PTR_ERR(priv->mmio);
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return ret;
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}
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priv->num_clks = phy_cfg->num_clks;
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priv->clks = devm_kmemdup(dev, phy_cfg->clks,
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phy_cfg->num_clks * sizeof(struct clk_bulk_data),
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GFP_KERNEL);
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if (!priv->clks)
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return -ENOMEM;
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priv->dev = dev;
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priv->mode = PHY_NONE;
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priv->cfg = phy_cfg;
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ret = rockchip_combphy_parse_dt(dev, priv);
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if (ret)
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return ret;
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priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create combphy\n");
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return PTR_ERR(priv->phy);
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}
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dev_set_drvdata(dev, priv);
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phy_set_drvdata(priv->phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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struct clk *refclk = NULL;
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unsigned long rate;
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int i;
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u32 val;
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/* Configure PHY reference clock frequency */
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for (i = 0; i < priv->num_clks; i++) {
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if (!strncmp(priv->clks[i].id, "refclk", 6)) {
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refclk = priv->clks[i].clk;
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break;
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}
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}
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if (!refclk) {
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dev_err(priv->dev, "No refclk found\n");
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return -EINVAL;
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}
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switch (priv->mode) {
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case PHY_TYPE_PCIE:
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/* Set SSC downward spread spectrum */
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val = readl(priv->mmio + 0x18);
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val &= ~GENMASK(5, 4);
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val |= 0x01 << 4;
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writel(val, priv->mmio + 0x18);
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param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
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param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
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break;
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case PHY_TYPE_USB3:
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/* Set SSC downward spread spectrum */
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val = readl(priv->mmio + 0x18);
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val &= ~GENMASK(5, 4);
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val |= 0x01 << 4;
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writel(val, priv->mmio + 0x18);
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/* Enable adaptive CTLE for USB3.0 Rx */
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val = readl(priv->mmio + 0x200);
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val &= ~GENMASK(17, 17);
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val |= 0x01 << 17;
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writel(val, priv->mmio + 0x200);
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/* Set slow slew rate control for PI */
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val = readl(priv->mmio + 0x204);
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val &= ~GENMASK(2, 0);
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val |= 0x07;
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writel(val, priv->mmio + 0x204);
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/* Set CDR phase path with 2x gain */
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val = readl(priv->mmio + 0x204);
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val &= ~GENMASK(5, 5);
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val |= 0x01 << 5;
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writel(val, priv->mmio + 0x204);
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/* Set Rx squelch input filler bandwidth */
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val = readl(priv->mmio + 0x20c);
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val &= ~GENMASK(2, 0);
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val |= 0x06;
|
|
writel(val, priv->mmio + 0x20c);
|
|
|
|
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
|
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
|
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
|
break;
|
|
default:
|
|
dev_err(priv->dev, "incompatible PHY type\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
rate = clk_get_rate(refclk);
|
|
|
|
switch (rate) {
|
|
case 24000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
|
|
if (priv->mode == PHY_TYPE_USB3) {
|
|
/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
|
|
val = readl(priv->mmio + 0x100);
|
|
val &= ~GENMASK(10, 0);
|
|
val |= 0x17d;
|
|
writel(val, priv->mmio + 0x100);
|
|
} else if (priv->mode == PHY_TYPE_PCIE) {
|
|
/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
|
|
val = readl(priv->mmio + 0x218);
|
|
val |= (1 << 14);
|
|
writel(val, priv->mmio + 0x218);
|
|
}
|
|
break;
|
|
case 100000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
|
if (priv->mode == PHY_TYPE_PCIE) {
|
|
/* PLL KVCO tuning fine */
|
|
val = readl(priv->mmio + 0x18);
|
|
val &= ~(0x7 << 10);
|
|
val |= 0x2 << 10;
|
|
writel(val, priv->mmio + 0x18);
|
|
|
|
/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
|
|
val = 0x570804f0;
|
|
writel(val, priv->mmio + 0x108);
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
|
|
/* pipe-phy-grf */
|
|
.pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 },
|
|
.usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 },
|
|
.pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 },
|
|
.pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 },
|
|
.pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 },
|
|
.pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 },
|
|
.pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 },
|
|
.pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 },
|
|
.pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 },
|
|
.pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 },
|
|
.pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 },
|
|
.pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 },
|
|
.con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 },
|
|
.con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 },
|
|
.con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 },
|
|
.con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 },
|
|
/* pipe-grf */
|
|
.u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 },
|
|
};
|
|
|
|
static const struct clk_bulk_data rk3528_clks[] = {
|
|
{ .id = "refclk" },
|
|
{ .id = "apbclk" },
|
|
{ .id = "pipe_clk" },
|
|
};
|
|
|
|
static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
|
|
.num_clks = ARRAY_SIZE(rk3528_clks),
|
|
.clks = rk3528_clks,
|
|
.grfcfg = &rk3528_combphy_grfcfgs,
|
|
.combphy_cfg = rk3528_combphy_cfg,
|
|
};
|
|
|
|
static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|
{
|
|
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
|
struct clk *refclk = NULL;
|
|
unsigned long rate;
|
|
int i;
|
|
u32 val;
|
|
|
|
/* Configure PHY reference clock frequency */
|
|
for (i = 0; i < priv->num_clks; i++) {
|
|
if (!strncmp(priv->clks[i].id, "refclk", 6)) {
|
|
refclk = priv->clks[i].clk;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!refclk) {
|
|
dev_err(priv->dev, "No refclk found\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (priv->mode) {
|
|
case PHY_TYPE_PCIE:
|
|
/* Set SSC downward spread spectrum */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(5, 4);
|
|
val |= 0x01 << 4;
|
|
writel(val, priv->mmio + 0x7c);
|
|
|
|
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
|
break;
|
|
case PHY_TYPE_USB3:
|
|
/* Set SSC downward spread spectrum */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(5, 4);
|
|
val |= 0x01 << 4;
|
|
writel(val, priv->mmio + 0x7c);
|
|
|
|
/* Enable adaptive CTLE for USB3.0 Rx */
|
|
val = readl(priv->mmio + (0x0e << 2));
|
|
val &= ~GENMASK(0, 0);
|
|
val |= 0x01;
|
|
writel(val, priv->mmio + (0x0e << 2));
|
|
|
|
/* Set PLL KVCO fine tuning signals */
|
|
val = readl(priv->mmio + (0x20 << 2));
|
|
val &= ~(0x7 << 2);
|
|
val |= 0x2 << 2;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
/* Set PLL LPF R1 to su_trim[10:7]=1001 */
|
|
writel(0x4, priv->mmio + (0xb << 2));
|
|
|
|
/* Set PLL input clock divider 1/2 */
|
|
val = readl(priv->mmio + (0x5 << 2));
|
|
val &= ~(0x3 << 6);
|
|
val |= 0x1 << 6;
|
|
writel(val, priv->mmio + (0x5 << 2));
|
|
|
|
/* Set PLL loop divider */
|
|
writel(0x32, priv->mmio + (0x11 << 2));
|
|
|
|
/* Set PLL KVCO to min and set PLL charge pump current to max */
|
|
writel(0xf0, priv->mmio + (0xa << 2));
|
|
|
|
/* Set Rx squelch input filler bandwidth */
|
|
writel(0x0e, priv->mmio + (0x14 << 2));
|
|
|
|
param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
|
|
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
|
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
|
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
|
break;
|
|
default:
|
|
dev_err(priv->dev, "incompatible PHY type\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
rate = clk_get_rate(refclk);
|
|
|
|
switch (rate) {
|
|
case 24000000:
|
|
if (priv->mode == PHY_TYPE_USB3) {
|
|
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
|
|
val = readl(priv->mmio + (0x0e << 2));
|
|
val &= ~GENMASK(7, 6);
|
|
val |= 0x01 << 6;
|
|
writel(val, priv->mmio + (0x0e << 2));
|
|
|
|
val = readl(priv->mmio + (0x0f << 2));
|
|
val &= ~GENMASK(7, 0);
|
|
val |= 0x5f;
|
|
writel(val, priv->mmio + (0x0f << 2));
|
|
}
|
|
break;
|
|
case 25000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
|
|
break;
|
|
case 100000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
|
if (priv->mode == PHY_TYPE_PCIE) {
|
|
/* PLL KVCO tuning fine */
|
|
val = readl(priv->mmio + (0x20 << 2));
|
|
val &= ~(0x7 << 2);
|
|
val |= 0x2 << 2;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
/* Enable controlling random jitter, aka RMJ */
|
|
writel(0x4, priv->mmio + (0xb << 2));
|
|
|
|
val = readl(priv->mmio + (0x5 << 2));
|
|
val &= ~(0x3 << 6);
|
|
val |= 0x1 << 6;
|
|
writel(val, priv->mmio + (0x5 << 2));
|
|
|
|
writel(0x32, priv->mmio + (0x11 << 2));
|
|
writel(0xf0, priv->mmio + (0xa << 2));
|
|
|
|
/* CKDRV output swing adjust to 650mv */
|
|
val = readl(priv->mmio + (0xd << 2));
|
|
val &= ~(0xf << 1);
|
|
val |= (0xb << 1);
|
|
writel(val, priv->mmio + (0xd << 2));
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
|
if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
|
|
val = readl(priv->mmio + (0xc << 2));
|
|
val |= 0x3 << 4 | 0x1 << 7;
|
|
writel(val, priv->mmio + (0xc << 2));
|
|
|
|
val = readl(priv->mmio + (0xd << 2));
|
|
val |= 0x1;
|
|
writel(val, priv->mmio + (0xd << 2));
|
|
}
|
|
}
|
|
|
|
if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
|
|
val = readl(priv->mmio + (0x7 << 2));
|
|
val |= BIT(4);
|
|
writel(val, priv->mmio + (0x7 << 2));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
|
|
/* pipe-phy-grf */
|
|
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
|
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
|
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
|
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
|
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
|
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
|
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
|
.pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
|
|
.pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
|
|
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
|
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
|
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
|
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
|
.pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
|
|
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
|
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
|
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
|
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
|
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
|
.pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 },
|
|
/* peri-grf */
|
|
.u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 },
|
|
};
|
|
|
|
static const struct clk_bulk_data rk3562_clks[] = {
|
|
{ .id = "refclk" },
|
|
{ .id = "apbclk" },
|
|
{ .id = "pipe_clk" },
|
|
};
|
|
|
|
static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
|
|
.num_clks = ARRAY_SIZE(rk3562_clks),
|
|
.clks = rk3562_clks,
|
|
.grfcfg = &rk3562_combphy_grfcfgs,
|
|
.combphy_cfg = rk3562_combphy_cfg,
|
|
.force_det_out = true,
|
|
};
|
|
|
|
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|
{
|
|
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
|
struct clk *refclk = NULL;
|
|
unsigned long rate;
|
|
int i;
|
|
u32 val;
|
|
|
|
/* Configure PHY reference clock frequency */
|
|
for (i = 0; i < priv->num_clks; i++) {
|
|
if (!strncmp(priv->clks[i].id, "refclk", 6)) {
|
|
refclk = priv->clks[i].clk;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!refclk) {
|
|
dev_err(priv->dev, "No refclk found\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (priv->mode) {
|
|
case PHY_TYPE_PCIE:
|
|
/* Set SSC downward spread spectrum */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(5, 4);
|
|
val |= 0x01 << 4;
|
|
writel(val, priv->mmio + 0x7c);
|
|
|
|
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
|
break;
|
|
case PHY_TYPE_USB3:
|
|
/* Set SSC downward spread spectrum */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(5, 4);
|
|
val |= 0x01 << 4;
|
|
writel(val, priv->mmio + 0x7c);
|
|
|
|
/* Enable adaptive CTLE for USB3.0 Rx */
|
|
val = readl(priv->mmio + (0x0e << 2));
|
|
val &= ~GENMASK(0, 0);
|
|
val |= 0x01;
|
|
writel(val, priv->mmio + (0x0e << 2));
|
|
|
|
/* Set PLL KVCO fine tuning signals */
|
|
val = readl(priv->mmio + (0x20 << 2));
|
|
val &= ~(0x7 << 2);
|
|
val |= 0x2 << 2;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
/* Set PLL LPF R1 to su_trim[10:7]=1001 */
|
|
writel(0x4, priv->mmio + (0xb << 2));
|
|
|
|
/* Set PLL input clock divider 1/2 */
|
|
val = readl(priv->mmio + (0x5 << 2));
|
|
val &= ~(0x3 << 6);
|
|
val |= 0x1 << 6;
|
|
writel(val, priv->mmio + (0x5 << 2));
|
|
|
|
/* Set PLL loop divider */
|
|
writel(0x32, priv->mmio + (0x11 << 2));
|
|
|
|
/* Set PLL KVCO to min and set PLL charge pump current to max */
|
|
writel(0xf0, priv->mmio + (0xa << 2));
|
|
|
|
/* Set Rx squelch input filler bandwidth */
|
|
writel(0x0d, priv->mmio + (0x14 << 2));
|
|
|
|
param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
|
|
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
|
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
|
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
|
break;
|
|
case PHY_TYPE_SATA:
|
|
writel(0x41, priv->mmio + 0x38);
|
|
writel(0x8F, priv->mmio + 0x18);
|
|
param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
|
param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
|
param_write(priv->phy_grf, &cfg->con2_for_sata, true);
|
|
param_write(priv->phy_grf, &cfg->con3_for_sata, true);
|
|
param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
|
|
break;
|
|
case PHY_TYPE_SGMII:
|
|
param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
|
param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
|
param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
|
param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
|
|
break;
|
|
case PHY_TYPE_QSGMII:
|
|
param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
|
param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
|
param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
|
|
param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
|
param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
|
|
break;
|
|
default:
|
|
dev_err(priv->dev, "incompatible PHY type\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
rate = clk_get_rate(refclk);
|
|
|
|
switch (rate) {
|
|
case 24000000:
|
|
if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
|
|
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
|
|
val = readl(priv->mmio + (0x0e << 2));
|
|
val &= ~GENMASK(7, 6);
|
|
val |= 0x01 << 6;
|
|
writel(val, priv->mmio + (0x0e << 2));
|
|
|
|
val = readl(priv->mmio + (0x0f << 2));
|
|
val &= ~GENMASK(7, 0);
|
|
val |= 0x5f;
|
|
writel(val, priv->mmio + (0x0f << 2));
|
|
}
|
|
break;
|
|
case 25000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
|
|
break;
|
|
case 100000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
|
if (priv->mode == PHY_TYPE_PCIE) {
|
|
/* PLL KVCO tuning fine */
|
|
val = readl(priv->mmio + (0x20 << 2));
|
|
val &= ~(0x7 << 2);
|
|
val |= 0x2 << 2;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
/* Enable controlling random jitter, aka RMJ */
|
|
writel(0x4, priv->mmio + (0xb << 2));
|
|
|
|
val = readl(priv->mmio + (0x5 << 2));
|
|
val &= ~(0x3 << 6);
|
|
val |= 0x1 << 6;
|
|
writel(val, priv->mmio + (0x5 << 2));
|
|
|
|
writel(0x32, priv->mmio + (0x11 << 2));
|
|
writel(0xf0, priv->mmio + (0xa << 2));
|
|
} else if (priv->mode == PHY_TYPE_SATA) {
|
|
/* downward spread spectrum +500ppm */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(7, 4);
|
|
val |= 0x50;
|
|
writel(val, priv->mmio + (0x1f << 2));
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
|
if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
|
|
val = readl(priv->mmio + (0xc << 2));
|
|
val |= 0x3 << 4 | 0x1 << 7;
|
|
writel(val, priv->mmio + (0xc << 2));
|
|
|
|
val = readl(priv->mmio + (0xd << 2));
|
|
val |= 0x1;
|
|
writel(val, priv->mmio + (0xd << 2));
|
|
}
|
|
}
|
|
|
|
if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
|
|
val = readl(priv->mmio + (0x7 << 2));
|
|
val |= BIT(4);
|
|
writel(val, priv->mmio + (0x7 << 2));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
|
|
/* pipe-phy-grf */
|
|
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
|
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
|
.sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
|
|
.qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
|
|
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
|
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
|
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
|
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
|
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
|
.pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
|
|
.pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
|
|
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
|
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
|
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
|
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
|
.pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
|
|
.pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
|
|
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
|
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
|
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
|
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
|
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
|
.con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
|
|
.con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
|
|
.con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
|
|
.con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
|
|
/* pipe-grf */
|
|
.pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
|
|
.pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 },
|
|
.pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
|
|
.u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 },
|
|
.u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 },
|
|
};
|
|
|
|
static const struct clk_bulk_data rk3568_clks[] = {
|
|
{ .id = "refclk" },
|
|
{ .id = "apbclk" },
|
|
{ .id = "pipe_clk" },
|
|
};
|
|
|
|
static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
|
|
.num_clks = ARRAY_SIZE(rk3568_clks),
|
|
.clks = rk3568_clks,
|
|
.grfcfg = &rk3568_combphy_grfcfgs,
|
|
.combphy_cfg = rk3568_combphy_cfg,
|
|
.force_det_out = true,
|
|
};
|
|
|
|
static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|
{
|
|
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
|
struct clk *refclk = NULL;
|
|
unsigned long rate;
|
|
int i;
|
|
u32 val;
|
|
|
|
/* Configure PHY reference clock frequency */
|
|
for (i = 0; i < priv->num_clks; i++) {
|
|
if (!strncmp(priv->clks[i].id, "refclk", 6)) {
|
|
refclk = priv->clks[i].clk;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!refclk) {
|
|
dev_err(priv->dev, "No refclk found\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (priv->mode) {
|
|
case PHY_TYPE_PCIE:
|
|
/* Set SSC downward spread spectrum */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(5, 4);
|
|
val |= 0x01 << 4;
|
|
writel(val, priv->mmio + 0x7c);
|
|
|
|
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
|
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
|
break;
|
|
case PHY_TYPE_USB3:
|
|
/* Set SSC downward spread spectrum */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(5, 4);
|
|
val |= 0x01 << 4;
|
|
writel(val, priv->mmio + 0x7c);
|
|
|
|
/* Enable adaptive CTLE for USB3.0 Rx */
|
|
val = readl(priv->mmio + (0x0e << 2));
|
|
val &= ~GENMASK(0, 0);
|
|
val |= 0x01;
|
|
writel(val, priv->mmio + (0x0e << 2));
|
|
|
|
/* Set PLL KVCO fine tuning signals */
|
|
val = readl(priv->mmio + (0x20 << 2));
|
|
val &= ~(0x7 << 2);
|
|
val |= 0x2 << 2;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
/* Set PLL LPF R1 to su_trim[10:7]=1001 */
|
|
writel(0x4, priv->mmio + (0xb << 2));
|
|
|
|
/* Set PLL input clock divider 1/2 */
|
|
val = readl(priv->mmio + (0x5 << 2));
|
|
val &= ~(0x3 << 6);
|
|
val |= 0x1 << 6;
|
|
writel(val, priv->mmio + (0x5 << 2));
|
|
|
|
/* Set PLL loop divider */
|
|
writel(0x32, priv->mmio + (0x11 << 2));
|
|
|
|
/* Set PLL KVCO to min and set PLL charge pump current to max */
|
|
writel(0xf0, priv->mmio + (0xa << 2));
|
|
|
|
/* Set Rx squelch input filler bandwidth */
|
|
writel(0x0d, priv->mmio + (0x14 << 2));
|
|
|
|
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
|
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
|
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
|
break;
|
|
case PHY_TYPE_SATA:
|
|
/* Enable adaptive CTLE for SATA Rx */
|
|
val = readl(priv->mmio + (0x0e << 2));
|
|
val &= ~GENMASK(0, 0);
|
|
val |= 0x01;
|
|
writel(val, priv->mmio + (0x0e << 2));
|
|
/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
|
|
writel(0x8F, priv->mmio + (0x06 << 2));
|
|
|
|
param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
|
param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
|
param_write(priv->phy_grf, &cfg->con2_for_sata, true);
|
|
param_write(priv->phy_grf, &cfg->con3_for_sata, true);
|
|
param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
|
|
param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
|
|
break;
|
|
case PHY_TYPE_SGMII:
|
|
case PHY_TYPE_QSGMII:
|
|
default:
|
|
dev_err(priv->dev, "incompatible PHY type\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
rate = clk_get_rate(refclk);
|
|
|
|
switch (rate) {
|
|
case 24000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
|
|
if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
|
|
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
|
|
val = readl(priv->mmio + (0x0e << 2));
|
|
val &= ~GENMASK(7, 6);
|
|
val |= 0x01 << 6;
|
|
writel(val, priv->mmio + (0x0e << 2));
|
|
|
|
val = readl(priv->mmio + (0x0f << 2));
|
|
val &= ~GENMASK(7, 0);
|
|
val |= 0x5f;
|
|
writel(val, priv->mmio + (0x0f << 2));
|
|
} else if (priv->mode == PHY_TYPE_PCIE) {
|
|
/* PLL KVCO tuning fine */
|
|
val = readl(priv->mmio + (0x20 << 2));
|
|
val &= ~GENMASK(4, 2);
|
|
val |= 0x4 << 2;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
/* Set up rx_trim */
|
|
val = 0x0;
|
|
writel(val, priv->mmio + (0x1b << 2));
|
|
|
|
/* Set up su_trim: T0_1 */
|
|
val = 0x90;
|
|
writel(val, priv->mmio + (0xa << 2));
|
|
val = 0x02;
|
|
writel(val, priv->mmio + (0xb << 2));
|
|
val = 0x57;
|
|
writel(val, priv->mmio + (0xd << 2));
|
|
|
|
val = 0x5f;
|
|
writel(val, priv->mmio + (0xf << 2));
|
|
}
|
|
break;
|
|
case 25000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
|
|
break;
|
|
case 100000000:
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
|
if (priv->mode == PHY_TYPE_PCIE) {
|
|
/* gate_tx_pck_sel length select work for L1SS */
|
|
val = 0xc0;
|
|
writel(val, priv->mmio + 0x74);
|
|
|
|
/* PLL KVCO tuning fine */
|
|
val = readl(priv->mmio + (0x20 << 2));
|
|
val &= ~GENMASK(4, 2);
|
|
val |= 0x4 << 2;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
|
|
val = 0x4c;
|
|
writel(val, priv->mmio + (0x1b << 2));
|
|
|
|
/* Set up su_trim: T3_P1 650mv */
|
|
val = 0x90;
|
|
writel(val, priv->mmio + (0xa << 2));
|
|
val = 0x43;
|
|
writel(val, priv->mmio + (0xb << 2));
|
|
val = 0x88;
|
|
writel(val, priv->mmio + (0xc << 2));
|
|
val = 0x56;
|
|
writel(val, priv->mmio + (0xd << 2));
|
|
} else if (priv->mode == PHY_TYPE_SATA) {
|
|
/* downward spread spectrum +500ppm */
|
|
val = readl(priv->mmio + (0x1f << 2));
|
|
val &= ~GENMASK(7, 4);
|
|
val |= 0x50;
|
|
writel(val, priv->mmio + (0x1f << 2));
|
|
|
|
/* ssc ppm adjust to 3500ppm */
|
|
val = readl(priv->mmio + (0x9 << 2));
|
|
val &= ~GENMASK(3, 0);
|
|
val |= 0x7;
|
|
writel(val, priv->mmio + (0x9 << 2));
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
|
|
param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
|
if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
|
|
val = 0x10;
|
|
writel(val, priv->mmio + (0x20 << 2));
|
|
|
|
val = 0x0c;
|
|
writel(val, priv->mmio + (0x1b << 2));
|
|
|
|
/* Set up su_trim: T3_P1 650mv */
|
|
val = 0x90;
|
|
writel(val, priv->mmio + (0xa << 2));
|
|
val = 0x43;
|
|
writel(val, priv->mmio + (0xb << 2));
|
|
val = 0x88;
|
|
writel(val, priv->mmio + (0xc << 2));
|
|
val = 0x56;
|
|
writel(val, priv->mmio + (0xd << 2));
|
|
}
|
|
}
|
|
|
|
if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
|
|
val = readl(priv->mmio + (0x7 << 2));
|
|
val |= BIT(4);
|
|
writel(val, priv->mmio + (0x7 << 2));
|
|
|
|
if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) {
|
|
/* Xin24M T0_1 650mV */
|
|
writel(0x00, priv->mmio + (0x10 << 2));
|
|
writel(0x32, priv->mmio + (0x11 << 2));
|
|
writel(0x00, priv->mmio + (0x1b << 2));
|
|
writel(0x90, priv->mmio + (0x0a << 2));
|
|
writel(0x02, priv->mmio + (0x0b << 2));
|
|
writel(0x08, priv->mmio + (0x0c << 2));
|
|
writel(0x57, priv->mmio + (0x0d << 2));
|
|
writel(0x40, priv->mmio + (0x0e << 2));
|
|
writel(0x5f, priv->mmio + (0x0f << 2));
|
|
writel(0x10, priv->mmio + (0x20 << 2));
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
|
|
/* pipe-phy-grf */
|
|
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
|
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
|
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
|
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
|
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
|
.pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
|
|
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
|
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
|
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
|
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
|
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
|
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
|
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
|
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
|
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
|
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
|
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
|
.con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
|
|
.con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
|
|
.con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
|
|
.con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
|
|
/* pipe-grf */
|
|
.pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
|
|
.pipe_con1_for_sata = { 0x0004, 2, 0, 0x00, 0x2 },
|
|
};
|
|
|
|
static const struct clk_bulk_data rk3588_clks[] = {
|
|
{ .id = "refclk" },
|
|
{ .id = "apbclk" },
|
|
{ .id = "phpclk" },
|
|
};
|
|
|
|
static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
|
|
.num_clks = ARRAY_SIZE(rk3588_clks),
|
|
.clks = rk3588_clks,
|
|
.grfcfg = &rk3588_combphy_grfcfgs,
|
|
.combphy_cfg = rk3588_combphy_cfg,
|
|
.force_det_out = true,
|
|
};
|
|
|
|
static const struct of_device_id rockchip_combphy_of_match[] = {
|
|
{
|
|
.compatible = "rockchip,rk3528-naneng-combphy",
|
|
.data = &rk3528_combphy_cfgs,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3562-naneng-combphy",
|
|
.data = &rk3562_combphy_cfgs,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3568-naneng-combphy",
|
|
.data = &rk3568_combphy_cfgs,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3588-naneng-combphy",
|
|
.data = &rk3588_combphy_cfgs,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
|
|
|
|
static struct platform_driver rockchip_combphy_driver = {
|
|
.probe = rockchip_combphy_probe,
|
|
.driver = {
|
|
.name = "naneng-combphy",
|
|
.of_match_table = rockchip_combphy_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(rockchip_combphy_driver);
|
|
|
|
MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
|
|
MODULE_LICENSE("GPL v2");
|