172 lines
5.2 KiB
C
172 lines
5.2 KiB
C
/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _M5253EVBE_H
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#define _M5253EVBE_H
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#define CONFIG_M5253EVBE /* define board type */
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#define CONFIG_MCFTMR
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#undef CONFIG_WATCHDOG /* disable watchdog */
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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#define CONFIG_ENV_OFFSET 0x4000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#else
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#define CONFIG_ENV_ADDR 0xffe04000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#endif
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text)
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/*
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* BOOTP options
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*/
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#undef CONFIG_BOOTP_BOOTFILESIZE
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#undef CONFIG_BOOTP_BOOTPATH
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#undef CONFIG_BOOTP_GATEWAY
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#undef CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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/* ATA */
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#define CONFIG_IDE_RESET 1
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#define CONFIG_IDE_PREINIT 1
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#define CONFIG_ATAPI
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#undef CONFIG_LBA48
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_IDE_MAXDEVICE 2
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#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0
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#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
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#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_MEMTEST_START 0x400
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#define CONFIG_SYS_MEMTEST_END 0x380000
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#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
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#define CONFIG_SYS_FAST_CLK
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#ifdef CONFIG_SYS_FAST_CLK
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# define CONFIG_SYS_PLLCR 0x1243E054
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# define CONFIG_SYS_CLK 140000000
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#else
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# define CONFIG_SYS_PLLCR 0x135a4140
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# define CONFIG_SYS_CLK 70000000
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#endif
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
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#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
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/*
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
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#ifdef CONFIG_MONITOR_IS_IN_RAM
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#define CONFIG_SYS_MONITOR_BASE 0x20000
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#else
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#endif
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
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#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
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/* FLASH organization */
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_SIZE 0x200000
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
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#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
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CF_ADDRMASK(2) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
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CF_CACR_DBWE)
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/* Port configuration */
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#define CONFIG_SYS_FECI2C 0xF0
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#define CONFIG_SYS_CS0_BASE 0xFFE00000
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#define CONFIG_SYS_CS0_MASK 0x001F0021
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#define CONFIG_SYS_CS0_CTRL 0x00001D80
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/*-----------------------------------------------------------------------
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* Port configuration
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*/
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#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
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#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
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#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
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#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
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#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
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#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
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#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
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#endif /* _M5253EVB_H */
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