125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_SYNOLOGY_DS414_H
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#define _CONFIG_SYNOLOGY_DS414_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
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* for DDR ECC byte filling in the SPL before loading the main
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* U-Boot into it.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x00800000
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/*
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* Commands configuration
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*/
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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/* SPI NOR flash default params, used by sf commands */
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#define CONFIG_SF_DEFAULT_SPEED 1000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
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/* Environment in SPI NOR flash */
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#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */
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#define CONFIG_PHY_ADDR { 0x1, 0x0 }
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#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
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#define CONFIG_SYS_ALT_MEMTEST
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/* PCIe support */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_PCI_MVEBU
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/* USB/EHCI/XHCI configuration */
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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/* FIXME: broken XHCI support
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* Below defines should enable support for the two rear USB3 ports. Sadly, this
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* does not work because:
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* - xhci-pci seems to not support DM_USB, so with that enabled it is not
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* found.
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* - USB init fails, controller does not respond in time */
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#if !defined(CONFIG_USB_XHCI_HCD)
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#define CONFIG_EHCI_IS_TDI
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#endif
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/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x40004030
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
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/* DS414 bus width is 32bits */
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#define CONFIG_DDR_32BIT
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/* Use random ethernet address if not configured */
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#define CONFIG_LIB_RAND
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#define CONFIG_NET_RANDOM_ETHADDR
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/* Default Environment */
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#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
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#define CONFIG_LOADADDR 0x80000
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#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
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#define CONFIG_PREBOOT "usb start; sf probe"
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#endif /* _CONFIG_SYNOLOGY_DS414_H */
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