149 lines
		
	
	
		
			3.7 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			149 lines
		
	
	
		
			3.7 KiB
		
	
	
	
		
			C
		
	
	
	
/*
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 * Configuration settings for the mini-box PICOSAM9G45 board.
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 * (C) Copyright 2015 Inter Act B.V.
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 *
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 * Based on:
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 * U-Boot file: include/configs/at91sam9m10g45ek.h
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 * (C) Copyright 2007-2008
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 * Stelian Pop <stelian@popies.net>
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 * Lead Tech Design <www.leadtechdesign.com>
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 *
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 * SPDX-License-Identifier:	GPL-2.0+
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 */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/hardware.h>
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#define CONFIG_SYS_TEXT_BASE		0x23f00000
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#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
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#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
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#define CONFIG_PICOSAM
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#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
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#define CONFIG_AT91_GPIO
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#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
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#define	CONFIG_USART_ID			ATMEL_ID_SYS
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/* LCD */
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#define LCD_BPP				LCD_COLOR8
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#define CONFIG_LCD_LOGO
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#undef LCD_TEST_PATTERN
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#define CONFIG_LCD_INFO
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#define CONFIG_LCD_INFO_BELOW_LOGO
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#define CONFIG_ATMEL_LCD
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#define CONFIG_ATMEL_LCD_RGB565
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/* board specific(not enough SRAM) */
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#define CONFIG_AT91SAM9G45_LCD_BASE		0x23E00000
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/* LED */
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#define CONFIG_AT91_LED
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#define CONFIG_GREEN_LED	AT91_PIN_PD31	/* this is the user1 led */
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/*
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 * BOOTP options
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 */
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/* Enable the watchdog */
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#define CONFIG_AT91SAM9_WATCHDOG
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#define CONFIG_HW_WATCHDOG
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/*
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 * Command line configuration.
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 */
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS	2
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#define PHYS_SDRAM_1		ATMEL_BASE_CS1	/* on DDRSDRC1 */
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#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
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#define PHYS_SDRAM_2		ATMEL_BASE_CS6	/* on DDRSDRC0 */
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#define PHYS_SDRAM_2_SIZE       0x08000000	/* 128 MB */
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#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR \
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	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* MMC */
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#endif
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT		20
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#define CONFIG_RESET_PHY_R
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#define CONFIG_AT91_WANTS_COMMON_PHY
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#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
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#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END		0x23e00000
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#ifdef CONFIG_SYS_USE_MMC
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/* bootstrap + u-boot + env + linux in mmc */
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#define CONFIG_ENV_SIZE		0x4000
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#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
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				"fatload mmc 0:1 0x22000000 zImage; " \
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				"bootz 0x22000000 - 0x21000000"
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#endif
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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/*
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 * Size of malloc() pool
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 */
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#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE		0x300000
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#define CONFIG_SPL_MAX_SIZE		0x010000
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#define CONFIG_SPL_STACK		0x310000
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#define CONFIG_SYS_MONITOR_LEN		0x80000
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_BSS_START_ADDR	0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
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#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
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#define CONFIG_SPL_ATMEL_SIZE
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#define CONFIG_SYS_MASTER_CLOCK		132096000
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#define CONFIG_SYS_AT91_PLLA		0x20c73f03
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#define CONFIG_SYS_MCKR			0x1301
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#define CONFIG_SYS_MCKR_CSS		0x1302
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#endif
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#endif
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