396 lines
12 KiB
C++
396 lines
12 KiB
C++
/*
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* Copyright (c) 2017-2018 Arm Limited.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef ARM_COMPUTE_TEST_HWC
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#define ARM_COMPUTE_TEST_HWC
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#include "hwc_names.hpp"
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#include <errno.h>
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#include <fcntl.h>
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#include <poll.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <unistd.h>
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#ifndef DOXYGEN_SKIP_THIS
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#if defined(ANDROID) || defined(__ANDROID__)
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/* We use _IOR_BAD/_IOW_BAD rather than _IOR/_IOW otherwise fails to compile with NDK-BUILD because of _IOC_TYPECHECK is defined, not because the paramter is invalid */
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#define MALI_IOR(a, b, c) _IOR_BAD(a, b, c)
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#define MALI_IOW(a, b, c) _IOW_BAD(a, b, c)
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#else /* defined(ANDROID) || defined(__ANDROID__) */
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#define MALI_IOR(a, b, c) _IOR(a, b, c)
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#define MALI_IOW(a, b, c) _IOW(a, b, c)
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#endif /* defined(ANDROID) || defined(__ANDROID__) */
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namespace mali_userspace
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{
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union uk_header
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{
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uint32_t id;
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uint32_t ret;
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uint64_t sizer;
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};
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#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3
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#define BASE_MAX_COHERENT_GROUPS 16
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struct mali_base_gpu_core_props
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{
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uint32_t product_id;
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uint16_t version_status;
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uint16_t minor_revision;
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uint16_t major_revision;
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uint16_t padding;
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uint32_t gpu_speed_mhz;
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uint32_t gpu_freq_khz_max;
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uint32_t gpu_freq_khz_min;
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uint32_t log2_program_counter_size;
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uint32_t texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
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uint64_t gpu_available_memory_size;
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};
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struct mali_base_gpu_l2_cache_props
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{
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uint8_t log2_line_size;
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uint8_t log2_cache_size;
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uint8_t num_l2_slices;
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uint8_t padding[5];
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};
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struct mali_base_gpu_tiler_props
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{
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uint32_t bin_size_bytes;
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uint32_t max_active_levels;
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};
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struct mali_base_gpu_thread_props
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{
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uint32_t max_threads;
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uint32_t max_workgroup_size;
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uint32_t max_barrier_size;
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uint16_t max_registers;
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uint8_t max_task_queue;
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uint8_t max_thread_group_split;
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uint8_t impl_tech;
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uint8_t padding[7];
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};
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struct mali_base_gpu_coherent_group
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{
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uint64_t core_mask;
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uint16_t num_cores;
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uint16_t padding[3];
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};
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struct mali_base_gpu_coherent_group_info
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{
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uint32_t num_groups;
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uint32_t num_core_groups;
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uint32_t coherency;
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uint32_t padding;
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mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
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};
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#define GPU_MAX_JOB_SLOTS 16
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struct gpu_raw_gpu_props
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{
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uint64_t shader_present;
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uint64_t tiler_present;
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uint64_t l2_present;
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uint64_t unused_1;
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uint32_t l2_features;
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uint32_t suspend_size;
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uint32_t mem_features;
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uint32_t mmu_features;
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uint32_t as_present;
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uint32_t js_present;
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uint32_t js_features[GPU_MAX_JOB_SLOTS];
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uint32_t tiler_features;
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uint32_t texture_features[3];
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uint32_t gpu_id;
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uint32_t thread_max_threads;
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uint32_t thread_max_workgroup_size;
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uint32_t thread_max_barrier_size;
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uint32_t thread_features;
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uint32_t coherency_mode;
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};
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struct mali_base_gpu_props
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{
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mali_base_gpu_core_props core_props;
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mali_base_gpu_l2_cache_props l2_props;
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uint64_t unused;
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mali_base_gpu_tiler_props tiler_props;
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mali_base_gpu_thread_props thread_props;
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gpu_raw_gpu_props raw_props;
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mali_base_gpu_coherent_group_info coherency_info;
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};
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struct kbase_uk_gpuprops
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{
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uk_header header;
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mali_base_gpu_props props;
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};
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#define KBASE_GPUPROP_VALUE_SIZE_U8 (0x0)
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#define KBASE_GPUPROP_VALUE_SIZE_U16 (0x1)
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#define KBASE_GPUPROP_VALUE_SIZE_U32 (0x2)
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#define KBASE_GPUPROP_VALUE_SIZE_U64 (0x3)
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#define KBASE_GPUPROP_PRODUCT_ID 1
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#define KBASE_GPUPROP_MINOR_REVISION 3
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#define KBASE_GPUPROP_MAJOR_REVISION 4
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#define KBASE_GPUPROP_COHERENCY_NUM_GROUPS 61
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#define KBASE_GPUPROP_COHERENCY_NUM_CORE_GROUPS 62
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#define KBASE_GPUPROP_COHERENCY_GROUP_0 64
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#define KBASE_GPUPROP_COHERENCY_GROUP_1 65
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#define KBASE_GPUPROP_COHERENCY_GROUP_2 66
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#define KBASE_GPUPROP_COHERENCY_GROUP_3 67
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#define KBASE_GPUPROP_COHERENCY_GROUP_4 68
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#define KBASE_GPUPROP_COHERENCY_GROUP_5 69
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#define KBASE_GPUPROP_COHERENCY_GROUP_6 70
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#define KBASE_GPUPROP_COHERENCY_GROUP_7 71
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#define KBASE_GPUPROP_COHERENCY_GROUP_8 72
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#define KBASE_GPUPROP_COHERENCY_GROUP_9 73
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#define KBASE_GPUPROP_COHERENCY_GROUP_10 74
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#define KBASE_GPUPROP_COHERENCY_GROUP_11 75
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#define KBASE_GPUPROP_COHERENCY_GROUP_12 76
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#define KBASE_GPUPROP_COHERENCY_GROUP_13 77
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#define KBASE_GPUPROP_COHERENCY_GROUP_14 78
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#define KBASE_GPUPROP_COHERENCY_GROUP_15 79
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struct gpu_props
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{
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uint32_t product_id;
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uint16_t minor_revision;
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uint16_t major_revision;
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uint32_t num_groups;
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uint32_t num_core_groups;
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uint64_t core_mask[16];
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};
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static const struct
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{
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uint32_t type;
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size_t offset;
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int size;
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} gpu_property_mapping[] =
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{
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#define PROP(name, member) \
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{ \
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KBASE_GPUPROP_##name, offsetof(struct gpu_props, member), \
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sizeof(((struct gpu_props *)0)->member) \
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}
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#define PROP2(name, member, off) \
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{ \
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KBASE_GPUPROP_##name, offsetof(struct gpu_props, member) + off, \
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sizeof(((struct gpu_props *)0)->member) \
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}
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PROP(PRODUCT_ID, product_id),
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PROP(MINOR_REVISION, minor_revision),
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PROP(MAJOR_REVISION, major_revision),
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PROP(COHERENCY_NUM_GROUPS, num_groups),
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PROP(COHERENCY_NUM_CORE_GROUPS, num_core_groups),
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PROP2(COHERENCY_GROUP_0, core_mask, 0),
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PROP2(COHERENCY_GROUP_1, core_mask, 1),
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PROP2(COHERENCY_GROUP_2, core_mask, 2),
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PROP2(COHERENCY_GROUP_3, core_mask, 3),
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PROP2(COHERENCY_GROUP_4, core_mask, 4),
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PROP2(COHERENCY_GROUP_5, core_mask, 5),
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PROP2(COHERENCY_GROUP_6, core_mask, 6),
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PROP2(COHERENCY_GROUP_7, core_mask, 7),
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PROP2(COHERENCY_GROUP_8, core_mask, 8),
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PROP2(COHERENCY_GROUP_9, core_mask, 9),
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PROP2(COHERENCY_GROUP_10, core_mask, 10),
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PROP2(COHERENCY_GROUP_11, core_mask, 11),
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PROP2(COHERENCY_GROUP_12, core_mask, 12),
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PROP2(COHERENCY_GROUP_13, core_mask, 13),
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PROP2(COHERENCY_GROUP_14, core_mask, 14),
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PROP2(COHERENCY_GROUP_15, core_mask, 15),
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#undef PROP
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#undef PROP2
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{ 0, 0, 0 }
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};
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struct kbase_hwcnt_reader_metadata
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{
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uint64_t timestamp = 0;
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uint32_t event_id = 0;
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uint32_t buffer_idx = 0;
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};
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namespace
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{
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/** Message header */
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union kbase_uk_hwcnt_header
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{
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/* 32-bit number identifying the UK function to be called. */
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uint32_t id;
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/* The int return code returned by the called UK function. */
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uint32_t ret;
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/* Used to ensure 64-bit alignment of this union. Do not remove. */
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uint64_t sizer;
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};
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/** IOCTL parameters to check version */
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struct kbase_uk_hwcnt_reader_version_check_args
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{
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union kbase_uk_hwcnt_header header;
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uint16_t major;
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uint16_t minor;
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uint8_t padding[4];
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};
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union kbase_pointer
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{
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void *value;
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uint32_t compat_value;
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uint64_t sizer;
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};
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struct kbase_ioctl_get_gpuprops
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{
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kbase_pointer buffer;
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uint32_t size;
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uint32_t flags;
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};
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#define KBASE_IOCTL_TYPE 0x80
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#define KBASE_IOCTL_GET_GPUPROPS MALI_IOW(KBASE_IOCTL_TYPE, 3, struct kbase_ioctl_get_gpuprops)
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/** IOCTL parameters to set flags */
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struct kbase_uk_hwcnt_reader_set_flags
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{
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union kbase_uk_hwcnt_header header;
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uint32_t create_flags;
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uint32_t padding;
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};
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/** IOCTL parameters to configure reader */
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struct kbase_uk_hwcnt_reader_setup
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{
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union kbase_uk_hwcnt_header header;
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/* IN */
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uint32_t buffer_count;
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uint32_t jm_bm;
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uint32_t shader_bm;
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uint32_t tiler_bm;
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uint32_t mmu_l2_bm;
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/* OUT */
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int32_t fd;
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};
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static const uint32_t HWCNT_READER_API = 1;
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struct uku_version_check_args
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{
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uk_header header;
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uint16_t major;
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uint16_t minor;
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uint8_t padding[4];
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};
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enum
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{
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UKP_FUNC_ID_CHECK_VERSION = 0,
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/* Related to mali0 ioctl interface */
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LINUX_UK_BASE_MAGIC = 0x80,
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BASE_CONTEXT_CREATE_KERNEL_FLAGS = 0x2,
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KBASE_FUNC_HWCNT_UK_FUNC_ID = 512,
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KBASE_FUNC_GPU_PROPS_REG_DUMP = KBASE_FUNC_HWCNT_UK_FUNC_ID + 14,
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KBASE_FUNC_HWCNT_READER_SETUP = KBASE_FUNC_HWCNT_UK_FUNC_ID + 36,
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KBASE_FUNC_HWCNT_DUMP = KBASE_FUNC_HWCNT_UK_FUNC_ID + 11,
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KBASE_FUNC_HWCNT_CLEAR = KBASE_FUNC_HWCNT_UK_FUNC_ID + 12,
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KBASE_FUNC_SET_FLAGS = KBASE_FUNC_HWCNT_UK_FUNC_ID + 18,
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/* The ids of ioctl commands for the reader interface */
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KBASE_HWCNT_READER = 0xBE,
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KBASE_HWCNT_READER_GET_HWVER = MALI_IOR(KBASE_HWCNT_READER, 0x00, uint32_t),
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KBASE_HWCNT_READER_GET_BUFFER_SIZE = MALI_IOR(KBASE_HWCNT_READER, 0x01, uint32_t),
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KBASE_HWCNT_READER_DUMP = MALI_IOW(KBASE_HWCNT_READER, 0x10, uint32_t),
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KBASE_HWCNT_READER_CLEAR = MALI_IOW(KBASE_HWCNT_READER, 0x11, uint32_t),
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KBASE_HWCNT_READER_GET_BUFFER = MALI_IOR(KBASE_HWCNT_READER, 0x20, struct kbase_hwcnt_reader_metadata),
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KBASE_HWCNT_READER_PUT_BUFFER = MALI_IOW(KBASE_HWCNT_READER, 0x21, struct kbase_hwcnt_reader_metadata),
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KBASE_HWCNT_READER_SET_INTERVAL = MALI_IOW(KBASE_HWCNT_READER, 0x30, uint32_t),
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KBASE_HWCNT_READER_ENABLE_EVENT = MALI_IOW(KBASE_HWCNT_READER, 0x40, uint32_t),
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KBASE_HWCNT_READER_DISABLE_EVENT = MALI_IOW(KBASE_HWCNT_READER, 0x41, uint32_t),
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KBASE_HWCNT_READER_GET_API_VERSION = MALI_IOW(KBASE_HWCNT_READER, 0xFF, uint32_t)
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};
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enum
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{
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PIPE_DESCRIPTOR_IN, /**< The index of a pipe's input descriptor. */
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PIPE_DESCRIPTOR_OUT, /**< The index of a pipe's output descriptor. */
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PIPE_DESCRIPTOR_COUNT /**< The number of descriptors forming a pipe. */
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};
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enum
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{
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POLL_DESCRIPTOR_SIGNAL, /**< The index of the signal descriptor in poll fds array. */
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POLL_DESCRIPTOR_HWCNT_READER, /**< The index of the hwcnt reader descriptor in poll fds array. */
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POLL_DESCRIPTOR_COUNT /**< The number of descriptors poll is waiting for. */
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};
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/** Write a single byte into the pipe to interrupt the reader thread */
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typedef char poll_data_t;
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}
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template <typename T>
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static inline int mali_ioctl(int fd, T &arg)
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{
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auto *hdr = &arg.header;
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const int cmd = _IOC(_IOC_READ | _IOC_WRITE, LINUX_UK_BASE_MAGIC, hdr->id, sizeof(T));
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if(ioctl(fd, cmd, &arg))
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return -1;
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if(hdr->ret)
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return -1;
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return 0;
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}
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} // namespace mali_userspace
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#endif /* DOXYGEN_SKIP_THIS */
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#endif /* ARM_COMPUTE_TEST_HWC */
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