556 lines
19 KiB
C
556 lines
19 KiB
C
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/spinlock.h>
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#include "../common/gic_common_private.h"
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#include "gicv2_private.h"
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static const gicv2_driver_data_t *driver_data;
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/*
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* Spinlock to guard registers needing read-modify-write. APIs protected by this
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* spinlock are used either at boot time (when only a single CPU is active), or
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* when the system is fully coherent.
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*/
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static spinlock_t gic_lock;
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/*******************************************************************************
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* Enable secure interrupts and use FIQs to route them. Disable legacy bypass
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* and set the priority mask register to allow all interrupts to trickle in.
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******************************************************************************/
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void gicv2_cpuif_enable(void)
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{
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unsigned int val;
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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/*
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* Enable the Group 0 interrupts, FIQEn and disable Group 0/1
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* bypass.
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*/
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val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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/* Program the idle priority in the PMR */
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gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK);
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gicc_write_ctlr(driver_data->gicc_base, val);
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}
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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void gicv2_cpuif_disable(void)
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{
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unsigned int val;
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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/* Disable secure, non-secure interrupts and disable their bypass */
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val = gicc_read_ctlr(driver_data->gicc_base);
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val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(driver_data->gicc_base, val);
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}
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/*******************************************************************************
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure SPIs and PPIs & enables them.
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******************************************************************************/
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void gicv2_pcpu_distif_init(void)
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{
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unsigned int ctlr;
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
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driver_data->interrupt_props,
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driver_data->interrupt_props_num);
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/* Enable G0 interrupts if not already */
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ctlr = gicd_read_ctlr(driver_data->gicd_base);
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if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) {
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gicd_write_ctlr(driver_data->gicd_base,
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ctlr | CTLR_ENABLE_G0_BIT);
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}
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}
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/*******************************************************************************
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* Global gic distributor init which will be done by the primary cpu after a
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* then enables the secure GIC distributor interface.
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******************************************************************************/
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void gicv2_distif_init(void)
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{
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unsigned int ctlr;
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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/* Disable the distributor before going further */
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ctlr = gicd_read_ctlr(driver_data->gicd_base);
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gicd_write_ctlr(driver_data->gicd_base,
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ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT));
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/* Set the default attribute of all SPIs */
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gicv2_spis_configure_defaults(driver_data->gicd_base);
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gicv2_secure_spis_configure_props(driver_data->gicd_base,
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driver_data->interrupt_props,
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driver_data->interrupt_props_num);
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/* Re-enable the secure SPIs now that they have been configured */
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gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT);
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}
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/*******************************************************************************
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* Initialize the ARM GICv2 driver with the provided platform inputs
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******************************************************************************/
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void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
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{
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unsigned int gic_version;
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assert(plat_driver_data != NULL);
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assert(plat_driver_data->gicd_base != 0U);
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assert(plat_driver_data->gicc_base != 0U);
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assert(plat_driver_data->interrupt_props_num > 0 ?
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plat_driver_data->interrupt_props != NULL : 1);
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/* Ensure that this is a GICv2 system */
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gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
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gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT)
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& PIDR2_ARCH_REV_MASK;
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/*
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* GICv1 with security extension complies with trusted firmware
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* GICv2 driver as far as virtualization and few tricky power
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* features are not used. GICv2 features that are not supported
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* by GICv1 with Security Extensions are:
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* - virtual interrupt support.
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* - wake up events.
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* - writeable GIC state register (for power sequences)
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* - interrupt priority drop.
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* - interrupt signal bypass.
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*/
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assert((gic_version == ARCH_REV_GICV2) ||
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(gic_version == ARCH_REV_GICV1));
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driver_data = plat_driver_data;
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/*
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* The GIC driver data is initialized by the primary CPU with caches
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* enabled. When the secondary CPU boots up, it initializes the
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* GICC/GICR interface with the caches disabled. Hence flush the
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* driver_data to ensure coherency. This is not required if the
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* platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
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* enabled.
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*/
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#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
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flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data));
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flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data));
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#endif
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INFO("ARM GICv2 driver initialized\n");
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}
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/******************************************************************************
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* This function returns whether FIQ is enabled in the GIC CPU interface.
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*****************************************************************************/
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unsigned int gicv2_is_fiq_enabled(void)
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{
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unsigned int gicc_ctlr;
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base);
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return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U;
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}
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/*******************************************************************************
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* This function returns the type of the highest priority pending interrupt at
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* the GIC cpu interface. The return values can be one of the following :
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* PENDING_G1_INTID : The interrupt type is non secure Group 1.
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* 0 - 1019 : The interrupt type is secure Group 0.
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* GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
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* sufficient priority to be signaled
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******************************************************************************/
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unsigned int gicv2_get_pending_interrupt_type(void)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
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}
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/*******************************************************************************
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* This function returns the id of the highest priority pending interrupt at
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* the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no
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* interrupt pending.
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******************************************************************************/
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unsigned int gicv2_get_pending_interrupt_id(void)
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{
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unsigned int id;
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
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/*
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* Find out which non-secure interrupt it is under the assumption that
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* the GICC_CTLR.AckCtl bit is 0.
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*/
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if (id == PENDING_G1_INTID)
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id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK;
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return id;
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}
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/*******************************************************************************
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* This functions reads the GIC cpu interface Interrupt Acknowledge register
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* to start handling the pending secure 0 interrupt. It returns the
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* contents of the IAR.
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******************************************************************************/
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unsigned int gicv2_acknowledge_interrupt(void)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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return gicc_read_IAR(driver_data->gicc_base);
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}
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/*******************************************************************************
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* This functions writes the GIC cpu interface End Of Interrupt register with
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* the passed value to finish handling the active secure group 0 interrupt.
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******************************************************************************/
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void gicv2_end_of_interrupt(unsigned int id)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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/*
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* Ensure the write to peripheral registers are *complete* before the write
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* to GIC_EOIR.
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*
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* Note: The completion gurantee depends on various factors of system design
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* and the barrier is the best core can do by which execution of further
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* instructions waits till the barrier is alive.
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*/
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dsbishst();
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gicc_write_EOIR(driver_data->gicc_base, id);
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}
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/*******************************************************************************
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* This function returns the type of the interrupt id depending upon the group
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* this interrupt has been configured under by the interrupt controller i.e.
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* group0 secure or group1 non secure. It returns zero for Group 0 secure and
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* one for Group 1 non secure interrupt.
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******************************************************************************/
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unsigned int gicv2_get_interrupt_group(unsigned int id)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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return gicd_get_igroupr(driver_data->gicd_base, id);
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}
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/*******************************************************************************
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* This function returns the priority of the interrupt the processor is
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* currently servicing.
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******************************************************************************/
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unsigned int gicv2_get_running_priority(void)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicc_base != 0U);
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return gicc_read_rpr(driver_data->gicc_base);
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}
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/*******************************************************************************
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* This function sets the GICv2 target mask pattern for the current PE. The PE
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* target mask is used to translate linear PE index (returned by platform core
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* position) to a bit mask used when targeting interrupts to a PE (for example
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* when raising SGIs and routing SPIs).
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******************************************************************************/
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void gicv2_set_pe_target_mask(unsigned int proc_num)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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assert(driver_data->target_masks != NULL);
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assert(proc_num < GICV2_MAX_TARGET_PE);
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assert(proc_num < driver_data->target_masks_num);
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/* Return if the target mask is already populated */
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if (driver_data->target_masks[proc_num] != 0U)
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return;
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/*
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* Update target register corresponding to this CPU and flush for it to
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* be visible to other CPUs.
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*/
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if (driver_data->target_masks[proc_num] == 0U) {
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driver_data->target_masks[proc_num] =
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gicv2_get_cpuif_id(driver_data->gicd_base);
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#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
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/*
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* PEs only update their own masks. Primary updates it with
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* caches on. But because secondaries does it with caches off,
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* all updates go to memory directly, and there's no danger of
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* secondaries overwriting each others' mask, despite
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* target_masks[] not being cache line aligned.
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*/
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flush_dcache_range((uintptr_t)
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&driver_data->target_masks[proc_num],
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sizeof(driver_data->target_masks[proc_num]));
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#endif
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}
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}
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/*******************************************************************************
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* This function returns the active status of the interrupt (either because the
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* state is active, or active and pending).
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******************************************************************************/
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unsigned int gicv2_get_interrupt_active(unsigned int id)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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assert(id <= MAX_SPI_ID);
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return gicd_get_isactiver(driver_data->gicd_base, id);
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}
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/*******************************************************************************
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* This function enables the interrupt identified by id.
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******************************************************************************/
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void gicv2_enable_interrupt(unsigned int id)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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assert(id <= MAX_SPI_ID);
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/*
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* Ensure that any shared variable updates depending on out of band
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* interrupt trigger are observed before enabling interrupt.
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*/
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dsbishst();
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gicd_set_isenabler(driver_data->gicd_base, id);
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}
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/*******************************************************************************
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* This function disables the interrupt identified by id.
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******************************************************************************/
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void gicv2_disable_interrupt(unsigned int id)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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assert(id <= MAX_SPI_ID);
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/*
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* Disable interrupt, and ensure that any shared variable updates
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* depending on out of band interrupt trigger are observed afterwards.
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*/
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gicd_set_icenabler(driver_data->gicd_base, id);
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dsbishst();
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}
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/*******************************************************************************
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* This function sets the interrupt priority as supplied for the given interrupt
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* id.
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******************************************************************************/
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void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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assert(id <= MAX_SPI_ID);
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gicd_set_ipriorityr(driver_data->gicd_base, id, priority);
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}
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/*******************************************************************************
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* This function assigns group for the interrupt identified by id. The group can
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* be any of GICV2_INTR_GROUP*
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******************************************************************************/
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void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
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{
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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assert(id <= MAX_SPI_ID);
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/* Serialize read-modify-write to Distributor registers */
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spin_lock(&gic_lock);
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switch (type) {
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case GICV2_INTR_GROUP1:
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gicd_set_igroupr(driver_data->gicd_base, id);
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break;
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case GICV2_INTR_GROUP0:
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gicd_clr_igroupr(driver_data->gicd_base, id);
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break;
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default:
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assert(false);
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break;
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}
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spin_unlock(&gic_lock);
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}
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/*******************************************************************************
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* This function raises the specified SGI to requested targets.
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*
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* The proc_num parameter must be the linear index of the target PE in the
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* system.
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******************************************************************************/
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void gicv2_raise_sgi(int sgi_num, int proc_num)
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{
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unsigned int sgir_val, target;
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assert(driver_data != NULL);
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assert(proc_num >= 0);
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assert(proc_num < (int)GICV2_MAX_TARGET_PE);
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assert(driver_data->gicd_base != 0U);
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/*
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* Target masks array must have been supplied, and the core position
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* should be valid.
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*/
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assert(driver_data->target_masks != NULL);
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assert(proc_num < (int)driver_data->target_masks_num);
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/* Don't raise SGI if the mask hasn't been populated */
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target = driver_data->target_masks[proc_num];
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assert(target != 0U);
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sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num);
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/*
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* Ensure that any shared variable updates depending on out of band
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* interrupt trigger are observed before raising SGI.
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*/
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dsbishst();
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gicd_write_sgir(driver_data->gicd_base, sgir_val);
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}
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/*******************************************************************************
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* This function sets the interrupt routing for the given SPI interrupt id.
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* The interrupt routing is specified in routing mode. The proc_num parameter is
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* linear index of the PE to target SPI. When proc_num < 0, the SPI may target
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* all PEs.
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******************************************************************************/
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void gicv2_set_spi_routing(unsigned int id, int proc_num)
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{
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unsigned int target;
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assert(driver_data != NULL);
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assert(driver_data->gicd_base != 0U);
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assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
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/*
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* Target masks array must have been supplied, and the core position
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* should be valid.
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*/
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assert(driver_data->target_masks != NULL);
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assert(proc_num < (int)GICV2_MAX_TARGET_PE);
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assert(driver_data->target_masks_num < INT_MAX);
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assert(proc_num < (int)driver_data->target_masks_num);
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if (proc_num < 0) {
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/* Target all PEs */
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target = GIC_TARGET_CPU_MASK;
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} else {
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/* Don't route interrupt if the mask hasn't been populated */
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target = driver_data->target_masks[proc_num];
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assert(target != 0U);
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}
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gicd_set_itargetsr(driver_data->gicd_base, id, target);
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}
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/*******************************************************************************
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* This function clears the pending status of an interrupt identified by id.
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******************************************************************************/
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void gicv2_clear_interrupt_pending(unsigned int id)
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{
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assert(driver_data != NULL);
|
|
assert(driver_data->gicd_base != 0U);
|
|
|
|
/* SGIs can't be cleared pending */
|
|
assert(id >= MIN_PPI_ID);
|
|
|
|
/*
|
|
* Clear pending interrupt, and ensure that any shared variable updates
|
|
* depending on out of band interrupt trigger are observed afterwards.
|
|
*/
|
|
gicd_set_icpendr(driver_data->gicd_base, id);
|
|
dsbishst();
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function sets the pending status of an interrupt identified by id.
|
|
******************************************************************************/
|
|
void gicv2_set_interrupt_pending(unsigned int id)
|
|
{
|
|
assert(driver_data != NULL);
|
|
assert(driver_data->gicd_base != 0U);
|
|
|
|
/* SGIs can't be cleared pending */
|
|
assert(id >= MIN_PPI_ID);
|
|
|
|
/*
|
|
* Ensure that any shared variable updates depending on out of band
|
|
* interrupt trigger are observed before setting interrupt pending.
|
|
*/
|
|
dsbishst();
|
|
gicd_set_ispendr(driver_data->gicd_base, id);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function sets the PMR register with the supplied value. Returns the
|
|
* original PMR.
|
|
******************************************************************************/
|
|
unsigned int gicv2_set_pmr(unsigned int mask)
|
|
{
|
|
unsigned int old_mask;
|
|
|
|
assert(driver_data != NULL);
|
|
assert(driver_data->gicc_base != 0U);
|
|
|
|
old_mask = gicc_read_pmr(driver_data->gicc_base);
|
|
|
|
/*
|
|
* Order memory updates w.r.t. PMR write, and ensure they're visible
|
|
* before potential out of band interrupt trigger because of PMR update.
|
|
*/
|
|
dmbishst();
|
|
gicc_write_pmr(driver_data->gicc_base, mask);
|
|
dsbishst();
|
|
|
|
return old_mask;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function updates single interrupt configuration to be level/edge
|
|
* triggered
|
|
******************************************************************************/
|
|
void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg)
|
|
{
|
|
gicd_set_icfgr(driver_data->gicd_base, id, cfg);
|
|
}
|