108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
/*
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* Copyright (c) 2017 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IPROC_QSPI_H
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#define IPROC_QSPI_H
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#include <platform_def.h>
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/*SPI configuration enable*/
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#define IPROC_QSPI_CLK_SPEED 62500000
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#define SPI_CPHA (1 << 0)
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#define SPI_CPOL (1 << 1)
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#define IPROC_QSPI_MODE0 0
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#define IPROC_QSPI_MODE3 (SPI_CPOL|SPI_CPHA)
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#define IPROC_QSPI_BUS 0
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#define IPROC_QSPI_CS 0
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#define IPROC_QSPI_BASE_REG QSPI_CTRL_BASE_ADDR
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#define IPROC_QSPI_CRU_CONTROL_REG QSPI_CLK_CTRL
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#define QSPI_AXI_CLK 200000000
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#define QSPI_RETRY_COUNT_US_MAX 200000
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/* Chip attributes */
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#define QSPI_REG_BASE IPROC_QSPI_BASE_REG
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#define CRU_CONTROL_REG IPROC_QSPI_CRU_CONTROL_REG
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#define SPBR_DIV_MIN 8U
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#define SPBR_DIV_MAX 255U
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#define NUM_CDRAM_BYTES 16U
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/* Register fields */
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#define MSPI_SPCR0_MSB_BITS_8 0x00000020
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/* Flash opcode and parameters */
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#define CDRAM_PCS0 2
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#define CDRAM_CONT (1 << 7)
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#define CDRAM_BITS_EN (1 << 6)
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#define CDRAM_QUAD_MODE (1 << 8)
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#define CDRAM_RBIT_INPUT (1 << 10)
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/* MSPI registers */
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#define QSPI_MSPI_MODE_REG_BASE (QSPI_REG_BASE + 0x200)
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#define MSPI_SPCR0_LSB_REG 0x000
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#define MSPI_SPCR0_MSB_REG 0x004
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#define MSPI_SPCR1_LSB_REG 0x008
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#define MSPI_SPCR1_MSB_REG 0x00c
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#define MSPI_NEWQP_REG 0x010
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#define MSPI_ENDQP_REG 0x014
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#define MSPI_SPCR2_REG 0x018
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#define MSPI_STATUS_REG 0x020
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#define MSPI_CPTQP_REG 0x024
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#define MSPI_TXRAM_REG 0x040
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#define MSPI_RXRAM_REG 0x0c0
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#define MSPI_CDRAM_REG 0x140
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#define MSPI_WRITE_LOCK_REG 0x180
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#define MSPI_DISABLE_FLUSH_GEN_REG 0x184
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#define MSPI_SPCR0_MSB_REG_MSTR_SHIFT 7
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#define MSPI_SPCR0_MSB_REG_16_BITS_PER_WD_SHIFT (0 << 2)
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#define MSPI_SPCR0_MSB_REG_MODE_MASK 0x3
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/* BSPI registers */
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#define QSPI_BSPI_MODE_REG_BASE QSPI_REG_BASE
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#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
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#define BSPI_BUSY_STATUS_REG 0x00c
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#define MSPI_CMD_COMPLETE_MASK 1
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#define BSPI_BUSY_MASK 1
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#define MSPI_CTRL_MASK 1
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#define MSPI_SPE (1 << 6)
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#define MSPI_CONT_AFTER_CMD (1 << 7)
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/* State */
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enum bcm_qspi_state {
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QSPI_STATE_DISABLED,
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QSPI_STATE_MSPI,
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QSPI_STATE_BSPI
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};
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/* QSPI private data */
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struct bcmspi_priv {
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/* Specified SPI parameters */
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uint32_t max_hz;
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uint32_t spi_mode;
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/* State */
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enum bcm_qspi_state state;
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int mspi_16bit;
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/* Registers */
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uintptr_t mspi_hw;
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uintptr_t bspi_hw;
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};
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int iproc_qspi_setup(uint32_t bus, uint32_t cs,
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uint32_t max_hz, uint32_t mode);
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int iproc_qspi_claim_bus(void);
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void iproc_qspi_release_bus(void);
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int iproc_qspi_xfer(uint32_t bitlen, const void *dout,
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void *din, unsigned long flags);
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#endif /* _IPROC_QSPI_H_ */
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