144 lines
3.5 KiB
C
144 lines
3.5 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <nxp_timer.h>
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#include <plat/common/platform.h>
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static uintptr_t g_nxp_timer_addr;
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static timer_ops_t ops;
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uint64_t get_timer_val(uint64_t start)
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{
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uint64_t cntpct;
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isb();
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cntpct = read_cntpct_el0();
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return (cntpct * 1000ULL / read_cntfrq_el0() - start);
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}
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static uint32_t timer_get_value(void)
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{
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uint64_t cntpct;
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isb();
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cntpct = read_cntpct_el0();
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#ifdef ERRATA_SOC_A008585
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uint8_t max_fetch_count = 10U;
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/* This erratum number needs to be confirmed to match ARM document */
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uint64_t temp;
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isb();
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temp = read_cntpct_el0();
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while (temp != cntpct && max_fetch_count) {
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isb();
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cntpct = read_cntpct_el0();
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isb();
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temp = read_cntpct_el0();
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max_fetch_count--;
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}
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#endif
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/*
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* Generic delay timer implementation expects the timer to be a down
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* counter. We apply bitwise NOT operator to the tick values returned
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* by read_cntpct_el0() to simulate the down counter. The value is
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* clipped from 64 to 32 bits.
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*/
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return (uint32_t)(~cntpct);
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}
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static void delay_timer_init_args(uint32_t mult, uint32_t div)
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{
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ops.get_timer_value = timer_get_value,
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ops.clk_mult = mult;
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ops.clk_div = div;
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timer_init(&ops);
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VERBOSE("Generic delay timer configured with mult=%u and div=%u\n",
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mult, div);
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}
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/*
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* Initialise the nxp on-chip free rolling usec counter as the delay
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* timer.
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*/
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void delay_timer_init(uintptr_t nxp_timer_addr)
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{
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/* Value in ticks */
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unsigned int mult = MHZ_TICKS_PER_SEC;
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unsigned int div;
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unsigned int counter_base_frequency = plat_get_syscnt_freq2();
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g_nxp_timer_addr = nxp_timer_addr;
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/* Rounding off the Counter Frequency to MHZ_TICKS_PER_SEC */
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if (counter_base_frequency > MHZ_TICKS_PER_SEC) {
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counter_base_frequency = (counter_base_frequency
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/ MHZ_TICKS_PER_SEC)
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* MHZ_TICKS_PER_SEC;
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} else {
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counter_base_frequency = (counter_base_frequency
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/ KHZ_TICKS_PER_SEC)
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* KHZ_TICKS_PER_SEC;
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}
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/* Value in ticks per second (Hz) */
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div = counter_base_frequency;
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/* Reduce multiplier and divider by dividing them repeatedly by 10 */
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while ((mult % 10U == 0U) && (div % 10U == 0U)) {
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mult /= 10U;
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div /= 10U;
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}
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/* Enable and initialize the System level generic timer */
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mmio_write_32(g_nxp_timer_addr + CNTCR_OFF,
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CNTCR_FCREQ(0) | CNTCR_EN);
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delay_timer_init_args(mult, div);
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}
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#ifdef IMAGE_BL31
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/*******************************************************************************
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* TBD: Configures access to the system counter timer module.
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******************************************************************************/
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void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base,
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uint8_t ls_config_cntacr,
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uint8_t plat_ls_ns_timer_frame_id)
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{
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unsigned int reg_val;
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if (ls_config_cntacr == 1U) {
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reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
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reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
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reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
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mmio_write_32(ls_sys_timctl_base +
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CNTACR_BASE(plat_ls_ns_timer_frame_id), reg_val);
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mmio_write_32(ls_sys_timctl_base, plat_get_syscnt_freq2());
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}
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reg_val = (1U << CNTNSAR_NS_SHIFT(plat_ls_ns_timer_frame_id));
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mmio_write_32(ls_sys_timctl_base + CNTNSAR, reg_val);
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}
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void enable_init_timer(void)
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{
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/* Enable and initialize the System level generic timer */
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mmio_write_32(g_nxp_timer_addr + CNTCR_OFF,
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CNTCR_FCREQ(0) | CNTCR_EN);
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}
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#endif
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