83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <rpi_hw.h>
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#include <drivers/rpi3/mailbox/rpi3_mbox.h>
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#define RPI3_MAILBOX_MAX_RETRIES U(1000000)
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/*******************************************************************************
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* Routine to send requests to the VideoCore using the mailboxes.
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******************************************************************************/
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void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size)
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{
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uint32_t st, data;
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uintptr_t resp_addr, addr;
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unsigned int retries;
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/* This is the location of the request buffer */
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addr = (uintptr_t)req;
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/* Make sure that the changes are seen by the VideoCore */
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flush_dcache_range(addr, req_size);
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/* Wait until the outbound mailbox is empty */
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retries = 0U;
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do {
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st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET);
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retries++;
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if (retries == RPI3_MAILBOX_MAX_RETRIES) {
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ERROR("rpi3: mbox: Send request timeout\n");
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return;
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}
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} while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U);
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/* Send base address of this message to start request */
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mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET,
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RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr);
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/* Wait until the inbound mailbox isn't empty */
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retries = 0U;
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do {
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st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET);
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retries++;
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if (retries == RPI3_MAILBOX_MAX_RETRIES) {
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ERROR("rpi3: mbox: Receive response timeout\n");
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return;
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}
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} while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U);
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/* Get location and channel */
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data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET);
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if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) {
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ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data);
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panic();
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}
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resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK);
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if (addr != resp_addr) {
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ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data);
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panic();
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}
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/* Make sure that the data seen by the CPU is up to date */
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inv_dcache_range(addr, req_size);
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}
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