126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CCI_H
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#define CCI_H
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#include <lib/utils_def.h>
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/* Slave interface offsets from PERIPHBASE */
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#define SLAVE_IFACE6_OFFSET UL(0x7000)
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#define SLAVE_IFACE5_OFFSET UL(0x6000)
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#define SLAVE_IFACE4_OFFSET UL(0x5000)
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#define SLAVE_IFACE3_OFFSET UL(0x4000)
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#define SLAVE_IFACE2_OFFSET UL(0x3000)
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#define SLAVE_IFACE1_OFFSET UL(0x2000)
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#define SLAVE_IFACE0_OFFSET UL(0x1000)
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#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
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(UL(0x1000) * (index)))
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/* Slave interface event and count register offsets from PERIPHBASE */
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#define EVENT_SELECT7_OFFSET UL(0x80000)
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#define EVENT_SELECT6_OFFSET UL(0x70000)
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#define EVENT_SELECT5_OFFSET UL(0x60000)
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#define EVENT_SELECT4_OFFSET UL(0x50000)
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#define EVENT_SELECT3_OFFSET UL(0x40000)
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#define EVENT_SELECT2_OFFSET UL(0x30000)
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#define EVENT_SELECT1_OFFSET UL(0x20000)
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#define EVENT_SELECT0_OFFSET UL(0x10000)
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#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
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(UL(0x10000) * (index)))
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/* Control and ID register offsets */
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#define CTRL_OVERRIDE_REG U(0x0)
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#define SECURE_ACCESS_REG U(0x8)
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#define STATUS_REG U(0xc)
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#define IMPRECISE_ERR_REG U(0x10)
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#define PERFMON_CTRL_REG U(0x100)
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#define IFACE_MON_CTRL_REG U(0x104)
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/* Component and peripheral ID registers */
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#define PERIPHERAL_ID0 U(0xFE0)
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#define PERIPHERAL_ID1 U(0xFE4)
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#define PERIPHERAL_ID2 U(0xFE8)
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#define PERIPHERAL_ID3 U(0xFEC)
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#define PERIPHERAL_ID4 U(0xFD0)
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#define PERIPHERAL_ID5 U(0xFD4)
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#define PERIPHERAL_ID6 U(0xFD8)
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#define PERIPHERAL_ID7 U(0xFDC)
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#define COMPONENT_ID0 U(0xFF0)
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#define COMPONENT_ID1 U(0xFF4)
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#define COMPONENT_ID2 U(0xFF8)
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#define COMPONENT_ID3 U(0xFFC)
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#define COMPONENT_ID4 U(0x1000)
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#define COMPONENT_ID5 U(0x1004)
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#define COMPONENT_ID6 U(0x1008)
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#define COMPONENT_ID7 U(0x100C)
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/* Slave interface register offsets */
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#define SNOOP_CTRL_REG U(0x0)
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#define SH_OVERRIDE_REG U(0x4)
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#define READ_CHNL_QOS_VAL_OVERRIDE_REG U(0x100)
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#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG U(0x104)
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#define MAX_OT_REG U(0x110)
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/* Snoop Control register bit definitions */
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#define DVM_EN_BIT BIT_32(1)
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#define SNOOP_EN_BIT BIT_32(0)
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#define SUPPORT_SNOOPS BIT_32(30)
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#define SUPPORT_DVM BIT_32(31)
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/* Status register bit definitions */
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#define CHANGE_PENDING_BIT BIT_32(0)
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/* Event and count register offsets */
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#define EVENT_SELECT_REG U(0x0)
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#define EVENT_COUNT_REG U(0x4)
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#define COUNT_CNTRL_REG U(0x8)
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#define COUNT_OVERFLOW_REG U(0xC)
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/* Slave interface monitor registers */
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#define INT_MON_REG_SI0 U(0x90000)
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#define INT_MON_REG_SI1 U(0x90004)
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#define INT_MON_REG_SI2 U(0x90008)
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#define INT_MON_REG_SI3 U(0x9000C)
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#define INT_MON_REG_SI4 U(0x90010)
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#define INT_MON_REG_SI5 U(0x90014)
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#define INT_MON_REG_SI6 U(0x90018)
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/* Master interface monitor registers */
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#define INT_MON_REG_MI0 U(0x90100)
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#define INT_MON_REG_MI1 U(0x90104)
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#define INT_MON_REG_MI2 U(0x90108)
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#define INT_MON_REG_MI3 U(0x9010c)
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#define INT_MON_REG_MI4 U(0x90110)
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#define INT_MON_REG_MI5 U(0x90114)
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#define SLAVE_IF_UNUSED -1
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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/* Function declarations */
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/*
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* The ARM CCI driver needs the following:
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* 1. Base address of the CCI product
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* 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave
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* interfaces.
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* 3. Size of the array.
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*
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* SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists
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* for that interface.
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*/
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void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters);
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void cci_enable_snoop_dvm_reqs(unsigned int master_id);
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void cci_disable_snoop_dvm_reqs(unsigned int master_id);
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#endif /* __ASSEMBLER__ */
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#endif /* CCI_H */
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