78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
/*
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* Copyright 2020-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DCFG_LSCH3_H
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#define DCFG_LSCH3_H
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/* dcfg block register offsets and bitfields */
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#define DCFG_PORSR1_OFFSET 0x00
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#define DCFG_DEVDISR1_OFFSET 0x70
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#define DCFG_DEVDISR1_SEC (1 << 22)
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#define DCFG_DEVDISR2_OFFSET 0x74
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#define DCFG_DEVDISR3_OFFSET 0x78
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#define DCFG_DEVDISR3_QBMAIN (1 << 12)
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#define DCFG_DEVDISR4_OFFSET 0x7C
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#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
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#define DCFG_DEVDISR5_OFFSET 0x80
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#define DISR5_DDRC1_MASK 0x1
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#define DISR5_DDRC2_MASK 0x2
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#define DISR5_OCRAM_MASK 0x1000
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#define DEVDISR5_MASK_ALL_MEM 0x00001003
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#define DEVDISR5_MASK_DDR 0x00000003
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#define DEVDISR5_MASK_DBG 0x00000400
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#define DCFG_DEVDISR6_OFFSET 0x84
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//#define DEVDISR6_MASK 0x00000001
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#define DCFG_COREDISR_OFFSET 0x94
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#define DCFG_SVR_OFFSET 0x0A4
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#define SVR_MFR_ID_MASK 0xF0000000
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#define SVR_MFR_ID_SHIFT 28
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#define SVR_FAMILY_MASK 0xF000000
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#define SVR_FAMILY_SHIFT 24
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#define SVR_DEV_ID_MASK 0x3F0000
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#define SVR_DEV_ID_SHIFT 16
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#define SVR_PERSONALITY_MASK 0x3E00
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#define SVR_PERSONALITY_SHIFT 9
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#define SVR_SEC_MASK 0x100
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#define SVR_SEC_SHIFT 8
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#define SVR_MAJ_VER_MASK 0xF0
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#define SVR_MAJ_VER_SHIFT 4
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#define SVR_MIN_VER_MASK 0xF
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#define RCWSR0_OFFSET 0x100
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#define RCWSR0_SYS_PLL_RAT_SHIFT 2
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#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define RCWSR0_MEM_PLL_RAT_SHIFT 10
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#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
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#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
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#define RCWSR5_OFFSET 0x110
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#define RCWSR9_OFFSET 0x120
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#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET
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#define RCWSR_SBEN_MASK 0x1
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#define RCWSR_SBEN_SHIFT 10
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#define RCW_SR27_OFFSET 0x168
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/* DCFG register to dump error code */
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#define DCFG_SCRATCH4_OFFSET 0x20C
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#define DCFG_SCRATCHRW5_OFFSET 0x210
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#define DCFG_SCRATCHRW6_OFFSET 0x214
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#define DCFG_SCRATCHRW7_OFFSET 0x218
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#define DCFG_BOOTLOCPTRL_OFFSET 0x400
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#define DCFG_BOOTLOCPTRH_OFFSET 0x404
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#define DCFG_COREDISABLEDSR_OFFSET 0x990
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#endif /* DCFG_LSCH3_H */
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