152 lines
3.4 KiB
C
152 lines
3.4 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DDR_H
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#define DDR_H
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#include "ddr_io.h"
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#include "dimm.h"
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#include "immap.h"
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#ifndef DDRC_NUM_CS
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#define DDRC_NUM_CS 4
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#endif
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/*
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* This is irrespective of what is the number of DDR controller,
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* number of DIMM used. This is set to maximum
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* Max controllers = 2
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* Max num of DIMM per controlle = 2
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* MAX NUM CS = 4
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* Not to be changed.
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*/
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#define MAX_DDRC_NUM 2
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#define MAX_DIMM_NUM 2
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#define MAX_CS_NUM 4
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#include "opts.h"
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#include "regs.h"
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#include "utility.h"
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#ifdef DDR_DEBUG
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#define debug(...) INFO(__VA_ARGS__)
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#else
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#define debug(...) VERBOSE(__VA_ARGS__)
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#endif
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#ifndef DDRC_NUM_DIMM
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#define DDRC_NUM_DIMM 1
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#endif
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#define CONFIG_CS_PER_SLOT \
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(DDRC_NUM_CS / DDRC_NUM_DIMM)
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/* Record of register values computed */
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struct ddr_cfg_regs {
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struct {
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unsigned int bnds;
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unsigned int config;
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unsigned int config_2;
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} cs[MAX_CS_NUM];
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unsigned int dec[10];
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unsigned int timing_cfg[10];
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unsigned int sdram_cfg[3];
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unsigned int sdram_mode[16];
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unsigned int md_cntl;
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unsigned int interval;
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unsigned int data_init;
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unsigned int clk_cntl;
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unsigned int init_addr;
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unsigned int init_ext_addr;
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unsigned int zq_cntl;
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unsigned int wrlvl_cntl[3];
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unsigned int ddr_sr_cntr;
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unsigned int sdram_rcw[6];
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unsigned int dq_map[4];
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unsigned int eor;
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unsigned int cdr[2];
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unsigned int err_disable;
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unsigned int err_int_en;
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unsigned int tx_cfg[4];
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unsigned int debug[64];
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};
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struct ddr_conf {
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int dimm_in_use[MAX_DIMM_NUM];
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int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */
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int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */
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unsigned long long cs_base_addr[MAX_CS_NUM];
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unsigned long long cs_size[MAX_CS_NUM];
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unsigned long long base_addr;
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unsigned long long total_mem;
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};
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struct ddr_info {
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unsigned long clk;
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unsigned long long mem_base;
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unsigned int num_ctlrs;
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unsigned int dimm_on_ctlr;
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struct dimm_params dimm;
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struct memctl_opt opt;
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struct ddr_conf conf;
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struct ddr_cfg_regs ddr_reg;
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struct ccsr_ddr *ddr[MAX_DDRC_NUM];
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uint16_t *phy[MAX_DDRC_NUM];
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int *spd_addr;
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unsigned int ip_rev;
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uintptr_t phy_gen2_fw_img_buf;
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void *img_loadr;
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int warm_boot_flag;
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};
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struct rc_timing {
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unsigned int speed_bin;
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unsigned int clk_adj;
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unsigned int wrlvl;
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};
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struct board_timing {
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unsigned int rc;
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struct rc_timing const *p;
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unsigned int add1;
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unsigned int add2;
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};
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enum warm_boot {
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DDR_COLD_BOOT = 0,
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DDR_WARM_BOOT = 1,
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DDR_WRM_BOOT_NT_SUPPORTED = -1,
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};
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int disable_unused_ddrc(struct ddr_info *priv, int mask,
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uintptr_t nxp_ccn_hn_f0_addr);
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int ddr_board_options(struct ddr_info *priv);
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int compute_ddrc(const unsigned long clk,
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const struct memctl_opt *popts,
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const struct ddr_conf *conf,
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struct ddr_cfg_regs *ddr,
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const struct dimm_params *dimm_params,
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const unsigned int ip_rev);
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int compute_ddr_phy(struct ddr_info *priv);
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int ddrc_set_regs(const unsigned long clk,
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const struct ddr_cfg_regs *regs,
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const struct ccsr_ddr *ddr,
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int twopass);
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int cal_board_params(struct ddr_info *priv,
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const struct board_timing *dimm,
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int len);
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/* return bit mask of used DIMM(s) */
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int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf);
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long long dram_init(struct ddr_info *priv
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#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
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, uintptr_t nxp_ccn_hn_f0_addr
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#endif
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);
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long long board_static_ddr(struct ddr_info *info);
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#endif /* DDR_H */
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