120 lines
2.8 KiB
C
120 lines
2.8 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DDR_OPTS_H
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#define DDR_OPTS_H
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#define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */
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#define DDR_BC4 4 /* burst chop */
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#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
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#define DDR_BL8 8 /* burst length 8 */
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#define DDR4_RTT_OFF 0
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#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
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#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
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#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
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#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
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#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
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#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
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#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
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#define DDR4_RTT_WR_OFF 0
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#define DDR4_RTT_WR_120_OHM 1
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#define DDR4_RTT_WR_240_OHM 2
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#define DDR4_RTT_WR_HZ 3
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#define DDR4_RTT_WR_80_OHM 4
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#define DDR_ODT_NEVER 0x0
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#define DDR_ODT_CS 0x1
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#define DDR_ODT_ALL_OTHER_CS 0x2
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#define DDR_ODT_OTHER_DIMM 0x3
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#define DDR_ODT_ALL 0x4
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#define DDR_ODT_SAME_DIMM 0x5
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#define DDR_ODT_CS_AND_OTHER_DIMM 0x6
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#define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
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#define DDR_BA_INTLV_CS01 0x40
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#define DDR_BA_INTLV_CS0123 0x64
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#define DDR_BA_NONE 0
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#define DDR_256B_INTLV 0x8
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struct memctl_opt {
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int rdimm;
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unsigned int dbw_cap_shift;
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struct local_opts_s {
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unsigned int auto_precharge;
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unsigned int odt_rd_cfg;
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unsigned int odt_wr_cfg;
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unsigned int odt_rtt_norm;
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unsigned int odt_rtt_wr;
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} cs_odt[DDRC_NUM_CS];
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int ctlr_intlv;
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unsigned int ctlr_intlv_mode;
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unsigned int ba_intlv;
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int addr_hash;
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int ecc_mode;
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int ctlr_init_ecc;
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int self_refresh_in_sleep;
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int self_refresh_irq_en;
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int dynamic_power;
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/* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
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unsigned int data_bus_dimm;
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unsigned int data_bus_used; /* on individual board */
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unsigned int burst_length; /* BC4, OTF and BL8 */
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int otf_burst_chop_en;
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int mirrored_dimm;
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int quad_rank_present;
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int output_driver_impedance;
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int ap_en;
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int x4_en;
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int caslat_override;
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unsigned int caslat_override_value;
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int addt_lat_override;
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unsigned int addt_lat_override_value;
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unsigned int clk_adj;
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unsigned int cpo_sample;
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unsigned int wr_data_delay;
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unsigned int cswl_override;
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unsigned int wrlvl_override;
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unsigned int wrlvl_sample;
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unsigned int wrlvl_start;
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unsigned int wrlvl_ctl_2;
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unsigned int wrlvl_ctl_3;
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int half_strength_drive_en;
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int twot_en;
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int threet_en;
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unsigned int bstopre;
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unsigned int tfaw_ps;
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int rtt_override;
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unsigned int rtt_override_value;
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unsigned int rtt_wr_override_value;
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unsigned int rtt_park;
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int auto_self_refresh_en;
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unsigned int sr_it;
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unsigned int ddr_cdr1;
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unsigned int ddr_cdr2;
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unsigned int trwt_override;
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unsigned int trwt;
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unsigned int twrt;
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unsigned int trrt;
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unsigned int twwt;
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unsigned int vref_phy;
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unsigned int vref_dimm;
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unsigned int odt;
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unsigned int phy_tx_impedance;
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unsigned int phy_atx_impedance;
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unsigned int skip2d;
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};
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#endif /* DDR_OPTS_H */
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