115 lines
3.4 KiB
C
115 lines
3.4 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_GICV3_H
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#define PLAT_GICV3_H
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#include <drivers/arm/gicv3.h>
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/* offset between redistributors */
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#define GIC_RD_OFFSET 0x00020000
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/* offset between SGI's */
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#define GIC_SGI_OFFSET 0x00020000
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/* offset from rd base to sgi base */
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#define GIC_RD_2_SGI_OFFSET 0x00010000
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/* register offsets */
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#define GICD_CTLR_OFFSET 0x0
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#define GICD_CLR_SPI_SR 0x58
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#define GICD_IGROUPR_2 0x88
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#define GICD_ISENABLER_2 0x108
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#define GICD_ICENABLER_2 0x188
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#define GICD_ICPENDR_2 0x288
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#define GICD_ICACTIVER_2 0x388
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#define GICD_IPRIORITYR_22 0x458
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#define GICD_ICFGR_5 0xC14
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#define GICD_IGRPMODR_2 0xD08
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#define GICD_IROUTER60_OFFSET 0x61e0
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#define GICD_IROUTER76_OFFSET 0x6260
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#define GICD_IROUTER89_OFFSET 0x62C8
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#define GICD_IROUTER112_OFFSET 0x6380
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#define GICD_IROUTER113_OFFSET 0x6388
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#define GICR_ICENABLER0_OFFSET 0x180
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#define GICR_CTLR_OFFSET 0x0
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#define GICR_IGROUPR0_OFFSET 0x80
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#define GICR_IGRPMODR0_OFFSET 0xD00
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#define GICR_IPRIORITYR3_OFFSET 0x40C
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#define GICR_ICPENDR0_OFFSET 0x280
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#define GICR_ISENABLER0_OFFSET 0x100
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#define GICR_TYPER_OFFSET 0x8
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#define GICR_WAKER_OFFSET 0x14
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#define GICR_ICACTIVER0_OFFSET 0x380
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#define GICR_ICFGR0_OFFSET 0xC00
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/* bitfield masks */
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#define GICD_CTLR_EN_GRP_MASK 0x7
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#define GICD_CTLR_EN_GRP_1NS 0x2
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#define GICD_CTLR_EN_GRP_1S 0x4
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#define GICD_CTLR_EN_GRP_0 0x1
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#define GICD_CTLR_ARE_S_MASK 0x10
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#define GICD_CTLR_RWP 0x80000000
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#define GICR_ICENABLER0_SGI15 0x00008000
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#define GICR_CTLR_RWP 0x8
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#define GICR_CTLR_DPG0_MASK 0x2000000
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#define GICR_IGROUPR0_SGI15 0x00008000
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#define GICR_IGRPMODR0_SGI15 0x00008000
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#define GICR_ISENABLER0_SGI15 0x00008000
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#define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000
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#define GICR_ICPENDR0_SGI15 0x8000
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#define GIC_SPI_89_MASK 0x02000000
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#define GIC_SPI89_PRIORITY_MASK 0xFF00
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#define GIC_IRM_SPI89 0x80000000
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#define GICD_IROUTER_VALUE 0x100
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#define GICR_WAKER_SLEEP_BIT 0x2
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#define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1)
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#define ICC_SRE_EL3_SRE 0x1
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#define ICC_IGRPEN0_EL1_EN 0x1
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#define ICC_CTLR_EL3_CBPR_EL1S 0x1
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#define ICC_CTLR_EL3_RM 0x20
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#define ICC_CTLR_EL3_EOIMODE_EL3 0x4
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#define ICC_CTLR_EL3_PMHE 0x40
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#define ICC_PMR_EL1_P_FILTER 0xFF
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#define ICC_IAR0_EL1_SGI15 0xF
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#define ICC_SGI0R_EL1_INTID 0x0F000000
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#define ICC_IAR0_INTID_SPI_89 0x59
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#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#ifndef __ASSEMBLER__
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/* GIC common API's */
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typedef unsigned int (*my_core_pos_fn)(void);
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void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
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const uintptr_t nxp_gicr_addr,
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uint8_t plat_core_count,
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interrupt_prop_t *ls_interrupt_props,
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uint8_t ls_interrupt_prop_count,
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uintptr_t *target_mask_array,
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mpidr_hash_fn mpidr_to_core_pos);
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//void plat_ls_gic_driver_init(void);
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void plat_ls_gic_init(void);
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void plat_ls_gic_cpuif_enable(void);
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void plat_ls_gic_cpuif_disable(void);
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void plat_ls_gic_redistif_on(void);
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void plat_ls_gic_redistif_off(void);
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void plat_gic_pcpu_init(void);
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#endif
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#endif /* PLAT_GICV3_H */
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