36 lines
761 B
C
36 lines
761 B
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#
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#ifndef NXP_TIMER_H
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#define NXP_TIMER_H
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/* System Counter Offset and Bit Mask */
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#define SYS_COUNTER_CNTCR_OFFSET 0x0
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#define SYS_COUNTER_CNTCR_EN 0x00000001
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#define CNTCR_EN_MASK 0x1
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#ifndef __ASSEMBLER__
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uint64_t get_timer_val(uint64_t start);
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#ifdef IMAGE_BL31
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void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base,
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uint8_t ls_config_cntacr,
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uint8_t plat_ls_ns_timer_frame_id);
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void enable_init_timer(void);
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#endif
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/*
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* Initialise the nxp on-chip free rolling usec counter as the delay
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* timer.
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*/
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void delay_timer_init(uintptr_t nxp_timer_addr);
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void ls_bl31_timer_init(uintptr_t nxp_timer_addr);
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#endif /* __ASSEMBLER__ */
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#endif /* NXP_TIMER_H */
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