56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2)
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#define PLAT_TZC400_H
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#include <tzc400.h>
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/* Structure to configure TZC Regions' boundaries and attributes. */
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struct tzc400_reg {
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uint8_t reg_filter_en;
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unsigned long long start_addr;
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unsigned long long end_addr;
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unsigned int sec_attr;
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unsigned int nsaid_permissions;
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};
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#define TZC_REGION_NS_NONE 0x00000000U
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/* NXP Platforms do not support NS Access ID (NSAID) based non-secure access.
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* Supports only non secure through generic NS ACCESS ID
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*/
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#define TZC_NS_ACCESS_ID 0xFFFFFFFFU
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/* Number of DRAM regions to be configured
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* for the platform can be over-written.
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*
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* Array tzc400_reg_list too, needs be over-written
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* if there is any changes to default DRAM region
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* configuration.
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*/
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#ifndef MAX_NUM_TZC_REGION
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/* 3 regions:
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* Region 0(default),
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* Region 1 (DRAM0, Secure Memory),
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* Region 2 (DRAM0, Shared memory)
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*/
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#define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3
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#define DEFAULT_TZASC_CONFIG 1
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#endif
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void mem_access_setup(uintptr_t base, uint32_t total_regions,
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struct tzc400_reg *tzc400_reg_list);
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int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
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int dram_idx, int list_idx,
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uint64_t dram_start_addr,
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uint64_t dram_size,
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uint32_t secure_dram_sz,
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uint32_t shrd_dram_sz);
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#endif /* PLAT_TZC400_H */
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